6-5 c ⃝ 2017 The Japan Society of Applied Physics 101 FinFET NBTI Degradation Reduction and Recovery Enhancement through Hydrogen Incorporation and Self-Heating Hiu Yung Wong*, Steve Motzny and Victor Moroz Synopsys, Inc. Mountain View, CA USA *hywong@synopsys.com Subrat Mishra and Souvik Mahapatra Department of Electrical Engineering Indian Institute of Technology Bombay Mumbai 400076, India Abstract — Negative-Bias Temperature Instability (NBTI) degrades the drive current of p-channel FinFET because defect centers are depassivated as hydrogen diffuses away under negative bias and elevated temperature. We propose incorporating hydrogen in the gate stack to reduce hydrogen depassivation rate and, thus, NBTI degradation. This approach is also expected to enhance NBTI recovery. Besides, we also propose using punch-through stop implant in bulk FinFET as an effective mean for on-chip self-heating and self-healing to enhance NBTI recovery. TCAD simulation is used to verify the ideas. Keywords — NBTI, TCAD Simulation, Hydrogen, Stress, Recovery I. INTRODUCTION Negative-Bias Temperature Instability (NBTI) remains an important degradation mechanism in sub- 22nm p-channel FinFETs and nano-wires [1][2][3]. NBTI means that the p-MOSFET’s threshold voltage (VTH) becomes more negative after ON-state operations (VG < 0V), resulting in lower drain current over time. The effect is exacerbated at elevated temperature when there is self-heating in the device. At VG = 0V, the devices usually experience recovery but the process is very slow. It would be very beneficial if the degradation can be reduced or the recovery can be enhanced. To reduce NBTI degradation, various methods have been proposed in the literature, including optimization of device geometries [1][2] and gate dielectric material engineering [4]. Since NBTI is due to electrochemical reaction involving hydrogen atoms and molecules as end products (Fig. 1), in this paper, we propose hydrogen incorporation in the gate stack to reduce degradation. At the same time, it is expected that this will also enhance recovery. Fig.1. Schematic showing the stack layers involved in the 3D FinFET NBTI simulations. Layer thicknesses are not in scale for clarity. Fig. 2. Experimental and simulated bulk FinFET degradation at different temperatures and gate voltages.