Microelectronics Journal, 23 (1992) 197-204 Self-Pruning Binary Tree Arch itectu res for Improved Interconnection Fault Tolerance ii~i~i~iii!i C. Sul, R. D. McLeod and W. Kinsner Departmentof Electrical and Computer Engineering, University of Manitoba, Winnipeg, Manitoba, Canada R3T 2N2 This paper proposes a self-pruning binary tree architecture to tolerate faults in a wafer scale integration (WSI) environment. The proposed architecture employs a bottom-up approach to recon- figure a linear pipelined array on a potentially defective WSI array using a binary tree interconnection scheme. The binary tree in the proposed architecture is generated by successive formation of hierarchical modules and can be laid out by using the H-tree layout. For N processing elements (PEs) on the wafer, reconfiguration time for this architecture is O(log N). The propagation delay is also bounded by O(log N) and is independent of the number of faulty PEs. This architecture achieves 100% PE utilization if the interconnections and the switch nodes are fauk-free. The proposed architecture is highly reliable because, by pruning faulty subtrees, it can tolerate up to ( N - 1) faulty PEs which may include clustered faults. 1. Introduction W " afer scale integration (WSI) has the potential for reducing cost and improving performance by assembling an entire system on a single wafer. To reach its full potential, architectures must be able to tolerate faults caused by defects on a wafer while retaining significant cost and performance advantages over individually packaged chips. This paper concentrates on architectures for linearly connected WSI arrays. Linear arrays permit efficient utilization of functional processing elements (PEs) on a wafer, with connection logic overhead smaller than in other configurations. Promising applications for linearly connected WSI arrays include linear systolic arrays, digital implementation of neural networks, and memory systems [1]. Several schemes have been proposed for embedding linear arrays. Manning [2], Aubusson and Catt [3], and Koren [4] introduced schemes to reconfigure hnear arrays on square-connected arrays. In these schemes, a chain is grown by joining the fault-free PEs from their nearest neighbors. The PE utilization (or harvest), defined as the number of utilized PEs over the number of functional PEs, is low for these schemes primarily due to the nearest neighbor restrictions [5]. Rosenberg [6] proposed the Diogenes scheme of bypassing failed PEs by using a set of buses which reconfigure both the PEs and the inter- connections with minimal overhead. Ramaswamy et al. [7] also proposed a scheme of bypassing failed 0026-2692/92/$5.00 © 1992, Elsevier Science Publishers Ltd. 197