Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning Swarup Bhunia, Hamid Mahmoodi, Debjyoti Ghosh, and Kaushik Roy Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907, USA Email: {bhunias, mahmoodi, dghosh, kaushik}@ecn.purdue.edu Abstract— Reduction in average and peak power during test application is important to improve battery lifetime in portable electronic devices employing periodic self-test and to improve reliability/cost of testing. This paper proposes an integrated solution for peak and average power reduction in test-per-scan BIST by targeting power reduction in both combinational block and scan chain. First, we present a novel circuit technique, called First Level Supply gating (FLS), to virtually eliminate power dissipation in combinational logic by masking signal transition at the logic inputs during scan shifting. We realize the masking effect by inserting an extra supply gating transistor in the VDD to GND path for the first level gates at the output of scan flip-flops. Simulation results on ISCAS89 benchmarks show an average reduction of 65% in area overhead, 119% in power overhead (in normal mode), and 104% in delay overhead compared to lowest-cost known signal masking alternative. To reduce the leakage power of the combinational block, which is considerably high in scaled technologies, we propose input vector control using FLS during scan shifting. Experiments on a set of ISCAS89 benchmarks show about 38% average reduction in leakage power with the proposed leakage reduction technique. Second, to address the power in the scan chain, we propose an efficient scan partitioning technique that reduces both average and peak power in the scan chain during shift and functional cycles. Experiments on a set of ISCAS89 benchmarks show 12.6% average reduction in peak power with the proposed partitioning method over partitioning according to RTL description. I. I NTRODUCTION Power dissipation during testing can be significantly higher than that during functional mode, since the input vectors dur- ing functional mode are usually strongly correlated compared to statistically independent consecutive input vectors during testing. Zorian in [1] showed that the test power could be twice as high as the power consumed during the normal mode. Test power is an important design concern to increase battery lifetime in hand-held electronic devices, that incorporate BIST circuitry for periodic self-test. It is also important to improve test cost, since reduced test power of a module allows parallel testing of multiple embedded cores in an IC [7]. Peak and average power reduction during test contributes to enhance reliability of test and hence, to improve yield. There are two components of power dissipation during testing: power in the combinational block and power in the scan chain. An integrated solution for low power test has to consider reduction in both components of test power. There has been multitude of research exploring efficient techniques to reduce test power in scan-based circuits. Wang et al. proposed automatic test pattern generation technique to reduce power dissipation during scan testing [3]. Scan-latch reordering [5] or input vector reordering [6] techniques have been proposed for reduction in test power. In [7], Whetsel provided a solution for average and peak power dissipation by transforming con- ventional scan architecture into desired number of selectable separate scan paths. Each scan path is in turn filled with stim- ulus and emptied of response. Sankaralingam et al. proposed a solution to the peak power problem during external testing by selectively disabling the scan chain [8]. These techniques, however, target reducing number of switching in the scan chain and cannot completely prevent redundant power loss in the combinational logic. Inserting blocking logic into the stimulus path of the scan cells to prevent propagation of scan-ripple effect to logic gates offers a simple and effective solution to significantly reduce test power in the combinational logic, independent of test set. Werstendorfer et al. have proposed NOR or NAND gate-based blocking method in [10]. Blocking gates (NOR or NAND) are controlled by the test enable signal and the stimulus paths remain fixed at either logic ‘0’ or logic ‘1’ during the entire scan shift operation. Zhang et al. have used multiplexers at the output of the scan cells, which hold the previous state of the scan register during shifting [11] and thus, prevent activity in the combinational logic. Another method for reducing combinational power using blocking is to use a scan- hold circuit as a sequential element. This technique, referred as enhanced scan [9], helps in delay fault testing by allowing application of an arbitrary two-pattern test. The problem with the blocking logic is that they add significant delay in the signal propagation path from the scan flip-flops to logic gates [10]. Moreover, they have large overhead in terms of area and switching power during normal operation of the circuit. In this paper, we propose a unified solution for test power reduction, which eliminates redundant power in combinational logic as well as minimizes power dissipation in the scan chain. In particular, the paper makes the following contributions: • We present an elegant signal blocking technique, referred to as First Level Supply gating or FLS, to reduce power dissipation in the combinational logic during scan shift- ing. This is achieved by selectively inserting a supply gating transistor in the first level of logic connected to the scan cell outputs, which essentially ”gates” the ripple in scan flip-flops. The proposed method is as effective as the other blocking methods in terms of reducing peak power and total energy dissipation during scan testing. Proceedings of the Sixth International Symposium on Quality Electronic Design (ISQED’05) 0-7695-2301-3/05 $ 20.00 IEEE Authorized licensed use limited to: San Francisco State Univ. Downloaded on December 10, 2008 at 21:01 from IEEE Xplore. Restrictions apply.