OxRAM integration above FDSOI transistor drain: Integration approach and process impact on electrical characteristics M. Barlas 1* , L. Grenouillet 1 , E. Vianello 1 , V. Delaye 1 , T. Dewolf 1 , G. Audoit 1 , N. Rambal 1 , S. Bernasconi 1 , C. Vizioz 1 , N. Posseme 1 , C. Arvet 2 , S. Barnola 1 , B. Bouix 1 , O. Pollet 1 , C. Comboroure 2 , N. Allouti 1 , P. Rodriguez 1 , V. Beugin 1 , V. Loup 1 , C. Tallaron 2 , S. Cheval- liez 1 , R. Coquand 1 , C. Jahan 1 , S. Reboh 1 , A. Toffoli 1 , S. Barraud 1 , L. Brevard 1 , Y. Morand 1 , M. Vinet 1 , O. Faynot 1 , and L. Perniola 1 1 CEA-Leti, Minatec Campus, 17 Rue de Martyrs, 38054 Grenoble, France 2 STMicroelectronics, Crolles, F-38920, France *E-mail: marios.barlas@cea.fr Abstract In this work, we present for the first time HfO2-based OxRAM co-integrated above the drain of FDSOI transistors at 300mm scale. Functional 1T-1R devices are demonstrated up to 10 8 cy- cles. The impact of process-induced structural defects in the electrical and statistical behavior of the devices is explained by means of simulation and TEM/EELS characterization, allowing to determine the requirements for more process-robust devices. 1. Introduction HfO2-based OxRAM are promising non-volatile memories with the capacity for integration both in the back-end and the front-end of HKMG CMOS technology owed to material compatibility [1, 2]. In- tegrating the memory element in the transistor vicinity can prove particularly beneficial for near memory computing architectures, not only as the best selector candidate to date is still the FET but also because it can enable high density, limit parasitic interconnect con- tributions and enable innovative, more flexible circuit design. In this context, we demonstrate a new OxRAM / FDSOI transistor co-inte- gration scheme and link the crosstalk between process and material related structural characteristics to the statistical behavior of the cells. 2. Integration approach The memory element is implemented right above the transistor drain in a 300 mm FDSOI route (Fig. 1), with 2 additional mask levels. For this first demonstration, the 1T-1R footprint is ~0.02 μm 2 , with thin oxide FDSOI transistor gate length and active width at 60 nm and 380 nm, respectively. The OxRAM structure consists of a TiN (30 nm)/Ti /HfO2 (5 nm, ALD deposited, amorphous)/TiN (10 nm) stack with Ti thickness splits of 5 nm and 10 nm. OxRAM ra- dius ranges from 500 nm down to 60 nm. A SiO2/SiN double-hard mask strategy is introduced for OxRAM stack patterning and serves a triple functionality: Firstly, it targets to minimize the impact of etching chemistry on the stack sidewalls by allowing oxygen-based dry stripping right after hard mask etching. Secondly, it enables sim- ultaneous contact opening at 3 different levels: transistor source, transistor gate, and OxRAM top electrode (Fig. 1). Finally, it allows patterning of nitride spacers around the stack aiming to protect Ox- RAM sidewalls with no impact on the hard mask. An STEM image of the developed 1T-1R structure is shown in Fig. 2. 3. Electrical characterization and statistical analysis The FDSOI transistors fabricated present good electrical behav- ior and very small threshold voltage dispersion (Fig. 3). Quasi-static and pulsed operation reaching up to 10 8 cycles of the memory cell is shown in Fig. 4a, and Fig. 4b for large structures. However, memory high resistive state (HRS) shows significant device-to-device varia- bility (Fig. 4b, grey zone). Forming voltage increases when device area decreases in line with already published results [3], and when the Ti oxygen scavenger thickness decreases (Fig. 5). However, Weibull statistics on the forming voltages show an unexpected be- havior: The Weibull slope which is expected to be constant with area [3, 4] decreases significantly with decreasing device area, with the trend becoming stronger for the thinner Ti stack (Fig. 6 a, b & Inset). This actively suggests a modification of the Ti/HfO2 interface prop- erties originating from the OxRAM sidewalls, as smaller devices are more strongly impacted. To get more insight on potential structural defects, TEM/EELS was performed for different OxRAM areas (Fig.7). 4. Impact of process-induced defects on Weibull Statistics TEM & EELS analysis reveals area-dependent cracking/delam- ination in the vicinity of the top TiN layer (Fig. 7 a, b), suggesting the presence of significant plane stress. Contact zone modeling (CZM) [5, 6] can reproduce the defect behavior as a function of the TiN/Ti interface adhesion properties [6, 8] and projected stress level in TiN. Analysis suggests that high compressive stress in TiN can catalyze the propagation of sidewall defects originating from the dry etch or wet process steps prior to memory encapsulation. Loss of contact is assumed at the sharp, PVD-deposited Ti/TiN junction owed to its high mechanical mismatch (Fig.8) that is expected to have inferior adhesion properties as compared to the mixed Ti/HfO2 interface [7]. Simulation shows that the derived crack propagation length is in-line with TEM observations (Fig. 7a, b & 9a-c) for TiN stress in the range of -6 GPa. This exposes the Ti layer to contami- nants such as oxygen (Fig. 7 c, d), impacting the Ti/HfO2 interface and therefore OxRAM electrical characteristics. Finally, the depend- ence of Weibull parameters to device area and Ti thickness can be attributed to a diffusion-limited segregation of oxygen towards the Ti/HfO2 interface limited by the crack extent and Ti layer thickness as well as a modification of the effective electrical surface of the cell. 5. Conclusions In this work, we present a new OxRAM integration, in the early MOL of a 300 mm FDSOI route. By Weibull analysis of the forming events, TEM/EELS analysis and simulation, we correlate the impact of structural defects originating from process steps and catalyzed by the pre-stressed TiN electrodes, to the quality of the Ti/HfO2 inter- face. Maintaining a trap-rich interface with strong adhesion as well as managing the structure stress level is critical for process-robust aggressively-scaled OxRAM with good electrical characteristics. References [1] M. Azzaz et al., ESSDERC 2015 [2] H.W. Pan et al., IEDM 2015 [3] B. Govoreanu et al., IEDM 2014 [4] E.Y. Wu, R.-P. Vollertsen, IEEE Trans. El. Dev. 49.12, 2131-2140, 2002 [5] P.P. Camanho, et al., J. Comp. mat. 37.16 (2003): 1415-1438. [6] J.R. Reeder, and J.R. Crews Jr., AiAA Journal 28.7 (1990): 1270-1276. [7] J. Colin et al., Philos. Mag. A, 75:2, 369-377, 1997 [8] J.W. Hutchinson, Z. Suo, Adv. In Appl. Mech (29), pp. ii-ix, 1-262, 1991 D-1-04 Extended Abstracts of the 2017 International Conference on Solid State Devices and Materials, Sendai, 2017, pp175-176 - 175 -