International Journal of Science and Research (IJSR) ISSN (Online): 2319-7064 Index Copernicus Value (2013): 6.14 | Impact Factor (2013): 4.438 Volume 4 Issue 8, August 2015 www.ijsr.net Licensed Under Creative Commons Attribution CC BY 8Kb Logic Compatible DRAM based Memory Design for Low Power Systems Harshita Shrivastava 1 , Rajesh Khatri 2 1,2 Department of Electronics & Instrumentation Engineering, Shree Govindram Seksaria Institute of Technology & Science Indore, India Abstract: 8Kb DRAM based memory is implemented for low power systems. 3T DRAM gain cell utilizing preferential boosting is used to achieve large data retention time and low leakage current which contributes to low power consumption. Current mode sense amplifier is designed for read operation to achieve high speed which gives output in voltage mode. There are two 4Kb sections in memory architecture which are controlled by internal control circuitry. This architecture has simplest write back circuitry. This Design performs all specific memory functions. This test memory has 20 pins. This design is done in 180nm CMOS technology Keywords: DRAM, Decoder, Sense amplifier, Control circuit, Logic gates. 1. Introduction Modern VLSI systems demands on chip memory. For better performance of system these memories should offer small size, fast operation and low power consumption. Random Access Memories are used as cash memories in systems, 6T Static Random Access Memories offer fast operation and are widely used for the same. As the increasing need of large memories 6T SRAM occupy large area as they use 6 MOS transistors to store one bit data, as an alternative Dynamic Random Access Memories are used to store data for large memories, which take lesser area and allows higher cell density. Along with less area DRAM cells offer low cost per bit. At the same time DRAM based memories have their drawback , these memories suffer poor data retention time due to leakage currents. Which results in loss of data. These leakage currents also contribute to high static power consumption. If data retention time is increased, by decreasing leakage current we can achieve less static power consumption. To overcome this problem of leakage current Luk et al. proposed a 3T1D gain cell where a gated-diode is used to preferentially boost the cell voltage via capacitive coupling [2]. But this approach uses an additional device and occupy large area another solution to achieve high data retention time was proposed by Ki Chul Chun[1] Which is used in this design. Memory architecture contributes to device performance and power consumption of the system[6]-[8]. This paper shows a controlling circuitry which is design to achieve low power consumption. This paper contains six sections. Section II explains basic DRAM structure and DRAM structure which is used in this paper. Sections III explains about sense amplifier and write back circuitry, section IV explains architecture and controlling circuitry. In section V Designed memory and Simulation results are discussed, and section VI gives conclusion. 2. Basic and Low Power Dram Cell Basic 3T DRAM structure is shown in Fig.1 (a) which has a write access transistor, read access transistor and a storage transistor. PMOS devices are chosen over NMOS devices because they have significantly less gate tunneling leakage current, which extends the data retention time [1]. When WWL signal switches to low logic level, WBL signal is transferred to storage node, when WWL signal again switches to high logic level, transferred WBL signal remains as stored data on gate capacitance of storage transistor . For read operation RBL is either pre- charged or pre-discharged based on the design of sense amplifier which gives the cell data by comparing the RBL with a reference read bit line. This basic 3T DRAM cell has its data retention time in the range of micro- seconds, and data is lost due to leakage currents flowing through transistors, to compensate this data loss DRAMs require time to time refreshing memory. This leakage current and refresh current contributes to large power consumption. Ki Chul Chun, Pulkit Jain and Chris H. Kim proposed a DRAM structure to increase data retention time without the need of any additional device [1]. which is shown in Fig.1(b) it has same working and storage mechanism as that of basic 3T DRAM cell here the source of storage transistor is connected to RWL which provides a stronger coupling effect. Hence improves data retention time and reduces the amount of leakage current thus it achieves low power consumption. Paper ID: SUB157372 1267