International Journal of Science and Research (IJSR) ISSN (Online): 2319-7064 Impact Factor (2012): 3.358 Volume 3 Issue 7, July 2014 www.ijsr.net Licensed Under Creative Commons Attribution CC BY Implementation of AES Algorithm in a Microblaze Processor Using System C Rudo Duri 1 , T. Madhavi Kumari 2 1 MTech, ECE Department, Jawaharlal Nehru Technological University, Hyderabad, India 2 Associate Professor, ECE Department, Jawaharlal Nehru Technological University, Hyderabad, India Abstract: This research investigates the Advanced Encryption Standard (AES) encryption and decryption algorithm with regard to 256- bit message length and 192- bit key length. In Spartan3 EDK we implemented the AES algorithm through pipelined architecture through the soft core processor, the Microblaze. Xilinx XC3S200 device of the Spartan family of the FPGA is used for hardware evaluation. The code is translated, mapped, placed and routed in Spartan 3 EDK using Xilinx Platform Studio (XPS). The microblaze processor is a RISC machine which is highly reconfigurable, uses 5-stage pipeline and has a 32-bit instruction word. By using system C coding the implementation makes it very low complexity architecture, that is, in saving the hardware resources. This implementation is most suited for hardware critical applications. Keywords: AES encryption, decryption, XPS, microblaze processor, system C, FPGA, Spartan. 1. Introduction For protection and security of sensitive information, encryption is becoming more and more important nowadays. Security of encrypted data depends on two things, the strength of the cryptographic key and the secrecy of the key while transmitting over a channel. AES offers greatest security to the sensitive data compared to other cryptographic algorithms. The AES was accepted as a standard in November 2001 [1]. NIST sought to “consider alternatives that offer a higher level of security” than that offered by the Data Encryption Standard (DES), [2], [3] which grew vulnerable to brute-force attacks due to its 56-bit effective key length. AES algorithm uses a varying cipher key size of 128, 192 and 256-bits to encrypt and decrypt data in blocks of 128-bits [4], [5]. Hardware based cryptography is considered superior to software based if implemented in a secure manner [6]. FPGAs provide a cost effective approach to building hardware accelerated computing platforms because they require lower development efforts and incur marginal nonrecurring engineering costs. The FPGA technology has much greater potential for providing higher security level because of its capability for dynamic reconfiguration [10], [12]. The FPGA uses highly pipelined architecture [13], and they are designed to overcome the limitations of existing micro processors and DSP processors. The paper is organized as follows; the description of AES encryption algorithm is discussed in section 2, followed by the decryption algorithm in section 3. Implementation is discussed in section 4, then results and conclusion in section 5 and 6 respectively. 1. AES Encryption Advanced Encryption Standard (AES) algorithm is a symmetric block cipher that encrypts and decrypts a 128-bit block message and a varying key size of 128, 192 and 256 bits. Encryption is a process of translating data into a secret code called ciphertext and decryption is converting ciphertext back to its readable format. The AES process consists of four stages that can be iterated a number of times depending on the size of key being used. For a key size of 128-bit, 10 rounds are required, 12 rounds for a 192-bit key and 14 rounds for a 256-bit key. These four stages are subBytes, shiftRows, mixColumns and addRoundKey. During encryption and decryption process the mixcolumn and invMixColumn processes are suppressed in the last rounds. If we take for instance, when using the AES-192, in the 12 th round the mixcolumn and the invmixcolumn will be missing in the encryption and decryption process respectively. The first three functions of an AES round are designed to thwart cryptanalysis via the methods of “confusion” and “diffusion.” The fourth function actually encrypts the data. Claude Shannon described the concepts of confusion and diffusion in his seminal 1949 paper, “Communication Theory of Secrecy Systems:” “Two methods suggest themselves for frustrating a statistical analysis. These we may call the methods of diffusion and confusion.” Confusion is making the relationship between the ciphertext and the key as complex and involving as possible and diffusion refers to dissipating the structure of the plaintext over bulk of the ciphertext Paper ID: 0201537 1815