IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 5, Issue 2, Ver. I (Mar. - Apr. 2015), PP 35-43 e-ISSN: 2319 – 4200, p-ISSN No. : 2319 – 4197 www.iosrjournals.org DOI: 10.9790/4200-05213543 www.iosrjournals.org 35 | Page The High performance Multiplexer based Adder Circuits Dr. K. Ragini a Professor,G. Narayanamma Institute of Technology & Science, Department of Electronics and Communication Engineering, Hyderabad, India Abstract: The need for extending low power circuits increased with the advent of use of large number of portable devices like cell phones, calculators, miniature computers etc. In all these devices, a long battery life is desired. An increase in battery life can be achieved by reducing power consumption of individual circuits. One of the methods to reduce the power consumption is by operating the devices at low current and low voltages. Operating the devices below threshold voltages is called as sub-threshold operation and the region of operation is called sub-threshold region. In this region, leakage current is used as operating current and power consumption is reduced significantly. The paper mainly focuses on the operation of various High performance Multiplexer based digital 1-bit Adder circuits[1] in sub-threshold region. The reduction in average power when compared to their super-threshold operation is analyzed. The variation of performance parameters and limitation of frequency of operation with variation in supply voltage are investigated. By varying the supply voltage below the threshold voltage, power can be reduced considerably. All the investigations in the paper are carried out using H-spice simulation tool. The circuits used are of 65nm process technology. Keywords: Sub-threshold , Propagation delay , Adder, power delay product, Power dissipation. I. Introduction Trends in semiconductor scaling have increased the difficulty in designing the devices that are in demand. Due to shrinking of transistor sizes, there is an increase in the growth of higher density devices which are resulted in power dissipation per chip to increase significantly. Smaller MOSFETs are desirable for several reasons. The main reason to make transistors smaller is to pack more and more devices in a given chip area. This results in a chip with the same functionality in a smaller area, or chips with more functionality in the same area. Since fabrication costs for a semiconductor wafer are relatively fixed, the cost per integrated circuits is mainly related to the number of chips that can be produced per wafer. Hence, smaller ICs allow more chips per wafer, reducing the price per chip. In fact, over the past 30 years the number of transistors per chip has been doubled every 2-3 years once a new technology node is introduced. For example, the number of MOSFETs in a microprocessor fabricated in a 45 nm technology can well be twice as many as in a 65 nm chip. This doubling of transistor density was first observed by Gordon Moore in 1965 and is commonly referred to as Moore's law . The ever-increasing density of MOSFETs on an integrated circuit creates problems of substantial localized heat generation that can impair circuit operation. Circuits operate more slowly at high temperatures, and have reduced reliability and shorter lifetimes. Heat sinks and other cooling methods are now required for many integrated circuits including microprocessors. The power dissipation problem facing the semiconductor industry has become so challenging. Without significant low power research efforts, new technologies may be needed as a long term solution. Reduction in power dissipation hence, is an important objective in the design of digital circuits. Well-known methods of low-power design (such as voltage scaling, switching activity reduction, architectural techniques of pipelining and parallelism) may not be sufficient in many applications such as portable computing gadgets, medical electronics, where ultra low-power consumption with medium frequency of operation (of the order of few MHz) is the primary requirement. Digital logic circuits computation using sub- threshold leakage current has gained a wide interest in recent years to achieve ultra low-power consumptions in portable computing devices. Both logic and memory circuits have been extensively studied with design consideration at various levels of abstraction. Significant power savings can be achieved in applications requiring low to medium frequency of operation using sub-threshold technique. The paper mainly focuses on achieving low power consumption by operating various circuits in the sub-threshold region[2]. The circuits considered are different 1-bit adder circuits which are compared[3] based on the performance metrics. 1.0 Sub-threshold 1-Bit Adder Circuits using 65nm Process Technology 1.1 Introduction: The 1-bit adder cell is one of the most critical components of a processor that determines its throughput, as it is used in the ALU, the floating point unit and for address generation in case of cache or memory access. Therefore, it is inherent that modifications made to the full adder cell affect the system as a