What to Lock? Functional and Parametric Locking Muhammad Yasin, Abhrajit Sengupta Electrical and Computer Engineering New York University {yasin,as9397}@nyu.edu Benjamin Carrion Schafer, Yiorgos Makris Electrical and Computer Engineering The University of Texas at Dallas {schaferb,yiorgos.makris}@utdallas.edu Ozgur Sinanoglu Electrical and Computer Engineering New York University Abu Dhabi ozgursin@nyu.edu Jeyavijayan (JV) Rajendran Electrical and Computer Engineering The University of Texas at Dallas jv.ee@utdallas.edu ABSTRACT Logic locking is an intellectual property (IP) protection tech- nique that prevents IP piracy, reverse engineering and over- building attacks by the untrusted foundry or end-users. Ex- isting logic locking techniques are all based on locking the functionality; the design/chip is nonfunctional unless the se- cret key has been loaded. Existing techniques are vulnera- ble to various attacks, such as sensitization, key-pruning, and signal skew analysis enabled removal attacks. In this paper, we propose a tenacious and traceless logic locking technique, TTlock, that locks functionality and provably withstands all known attacks, such as SAT-based, sensitiza- tion, removal, etc. TTLock protects a secret input pattern; the output of a logic cone is flipped for that pattern, where this flip is restored only when the correct key is applied. Experimental results confirm our theoretical expectations that the computational complexity of attacks launched on TTLock grows exponentially with increasing key-size, while the area, power, and delay overhead increases only linearly. In this paper, we also coin “parametric locking,” where the design/chip behaves as per its specifications (performance, power, reliability, etc.) only with the secret key in place, and an incorrect key downgrades its parametric characteristics. We discuss objectives and challenges in parametric locking. 1. INTRODUCTION Today’s integrated circuits (ICs) are designed and fabri- cated in a globalized, multi-vendor environment due to the high cost of building and maintaining a foundry [1]. Further, to meet strict time-to-market constraints, a design company may purchase intellectual property (IP) cores from third- party IP vendors. A globalized IC supply chain allows for the crucial assets to be handled by untrustworthy agents and creates opportunities for IP/IC piracy, reverse engineering, Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third- party components of this work must be honored. For all other uses, contact the Owner/Author(s). Copyright is held by the owner/author(s). GLSVLSI ’17, May 10-12, 2017, Banff, AB, Canada c  2017 ACM. 978-1-4503-4972-7/17/05 ...$15.00 DOI: http://dx.doi.org/10.1145/3060403.3060492. G1 G2 G3 G5 a b c PO G4 (a) Example circuit [12]. G1 G2 G3 G5 a b c PO K3 K1 K2 G K1 G K2 G K3 Tamper2proof Memory G4 (b) Circuit locked using XOR/XNOR key gates. The correct key {K1,K2,K3} value is 100. Figure 1: Functional logic locking using XOR/XNOR gates [6]. counterfeiting, and malicious modifications to the IC in the form of hardware Trojans [2,3]. To thwart such attacks, countermeasures such as IC cam- ouflaging [4] and split manufacturing [5] have been devel- oped. IC camouflaging and split manufacturing protect only against the untrusted user and untrusted foundry, respec- tively. Logic locking is a technique that thwarts IP piracy, overbuilding, and reverse engineering attacks by locking a chip with a secret key [6–11]. To enable chip-locking fea- tures, additional logic, e.g., XOR/XNORs gates referred to as key-gates, is added to the original netlist to obtain a locked netlist. Logic locking protects against both untrusted foundry and user. The secret key needs to be loaded for the design/chip to become functional; otherwise, the chip pro- duces incorrect outputs. Logic locking techniques lock the functionality of the design/chip. Figure 1(a) shows an example design netlist of a circuit, and Figure 1(b) shows its functionally locked version through two XOR and one XNOR key-gates. One of the inputs of each key-gate is driven by a wire in the original design, while the other input, referred to as the key-input, is driven by a key-bit stored in a tamper-proof memory. Logic locking aims to deliver the following protection: (i) Without the knowledge of the secret key, exact design details cannot be retrieved, and (ii) A locked IC (or a locked netlist) will not generate correct output unless it is activated, i.e., the secret key is loaded onto the chip’s memory. 351