System-Level Modelling for Reconfigurable SoCs I. Benkermi * , A. Benkhelifa † , D. Chillet * , S. Pillement * , J.C. Prévotet † , F. Verdier † * ENSSAT – Université de Rennes I, IRISA, 6, rue de Kerampont - 22300 Lannion - France † ETIS – UMR 8051 – Université de Cergy-Pontoise, ENSEA, 6, Avenue du Ponceau - 95014 Cergy-Pontoise - France Abstract— The integration of dynamically reconfigurable mod- ules into systems-on-chip ensures a certain degree of flexibility. In fact, it allows systems-on-chip to adapt to variable computation loads, due to the beginning of new tasks or to data dependent processings, for example. In order to get the most advantages of these reconfigurable modules, the operating system must provide the different tasks placement on available targets. This operation has to be performed on-line and must take into account the heterogeneousness of these different targets (software and hardware). In addition, a validation phase is necessary due to the complexity of these applications and systems. This validation can be done on a prototyping platform taking into account the entire system component set. To do so, a general simulation model must be available to evaluate performance application on the chip. The goal of this paper is to propose a general model of a system-on-chip based platform which includes dynamically reconfigurable modules. This model is essential prior to the implementation phase of an application and aims at providing a real simulation framework. The proposed model includes the entire system, that is, the applicative level, the middleware level and the architectural level. The model notably describes the interactions between the operating system and the reconfigurable modules and defines specific services according to the originality of the considered platform. A UML formalism has been chosen for the model description, in order to take advantage of the object oriented framework. I. I NTRODUCTION Nowadays, algorithmic complexity of applications tends to increase in many domains such as signal, image processing or control. In parallel, embedded applications require a significant power of calculation in order to satisfy demanding real time constraints. This leads designers to opt for hardware architec- tures composed of heterogeneous, optimized computation units operating in parallel. Hardware components in SOC (System on Chip) may implement programmable computation units, dedicated or reconfigurable units, or even dedicated datapaths. In particular, reconfigurable units (e.g FPGA, DART [3]), denoted here as Dynamically Reconfigurable Accelerators (DRA), allow an architecture to adapt to various incoming tasks or to various computation charge due to data depen- dencies treatments. The Platform-Based Design methodol- ogy [6] may thus be fully respected, adding flexibility to an architecture towards modifications of its functionality or even the environment (changing standards, mission statements, etc.). This flexibility is provided by the dynamic allocation of different and dedicated processing operators within the DRA. On the other hand, such heterogeneous architectures need even more complex management and control. In this context, the utilization of an RTOS (Real Time Operating System) is more and more required to furnish services such as communications, memory management, task scheduling and placement. These services have to be fulfilled in real time according to the application constraints. Moreover, such an operating system also provides a complete design framework which is independent of the technology and of the hardware architecture, drastically reducing the time to market. Embedded RTOS for SOCs has been of great interest and has led to several significant studies. In the context of reconfigurable architectures, a study of [4] has determined and classified the different services that operating systems should provide to handle reconfigurability. Today, two different approaches have emerged. The first consists in utilizing a pre- existent standard RTOS (RTAI [14], RTLinux, VxWorks, ...) and in adding functionnalities dedicated to the management of the reconfigurable resources [10], [9]. The second is to develop a specific RTOS from scratch by implementing the necessary functionalities devoted to the management of the reconfigurable part [19], [16], [17]. To study the interaction between operating system and SOC architecture, and particulary with dynamically reconfigurable modules, we propose to develop a platform model. The goal of this paper is to present our RSoC (Reconfigurable System on Chip) platform model, that includes the whole set of software and hardware elements and their interactions. This article first aims at identifying the different software and hardware components operating in these architectures. Specifically, its purpose is to define the role and the organization of the middleware layer. The main goal is to obtain formal criteria to develop an operating system deeply adapted to this type of architecture. This allows the software and hardware designers that are interested in RSoC to work on the same basis and to focus on the specificity of reconfigurable systems. The concern of delivering the most generic model as possible, supporting a wide varieties of platforms, has led us to adopt a formalism based on UML. Section II of this article introduces the context of application deployments on a RSoC. In the section III the global model is proposed and the different levels of representation are defined. Some OS services definitions for RSoC management are also listed in this section. Finally, section IV concludes and draws the perspectives of the current work.