Power Gating Design for Standard-Cell-Like Structured ASICs Sin-Yu Chen, Rung-Bin Lin, Hui-Hsiang Tung, and Kuen-Wey Lin Computer Science and Engineering line Yuan Ze University Chung-Li, Taiwan Abstract—Structured ASIC has been introduced to bridge the power, performance, area and design cost gaps between ASIC and FPGA. As technology scales, leakage power consumption becomes a serious problem. Among the leakage power reduction techniques, power gating is commonly used to disconnect idle logic blocks from power network to curtail sub-threshold leakage. In this paper, we apply power gating to structured ASICs for leakage power reduction. We present a power-gated via-configurable logic block (PGVCLB) and a power gated design flow mostly using existing standard cell design tools. We can configure PGVCLBs in a design to implement fine-grained power gating, coarse-grained/cluster-based power gating or even distributed sleep transistor network (DSTN). With fine-grained power gating, we can achieve 52% leakage reduction on average with only 8% area and 17% delay overheads when compared to the data obtained using a non-power-gated library. Keywords: power-gating, low power, via-configurable, structured ASIC. I. INTRODUCTION Structured ASIC is a design style that can bridge the performance, power, area, and design cost gaps between ASIC and FPGA [1-7]. It contains arrays of via-configurable logic blocks (VCLB) with prefabricated transistors and possibly predefined yet via-configurable metal wires [8-17]. Its engineering change order (ECO) cost is considerably smaller than that for ASIC. Its ECO cost mainly involves customizing a few relatively inexpensive via masks, each of which requires far fewer shots than a metal-wire mask does. Its regular layout structure also enables a higher and more predictable manufacturing yield. Many researches have been done to make structured ASIC more viable. These researches mainly focus on exploring VCLB architectures. Some of these researches also perform routing architecture exploration using their own structured ASIC routers [9,16,17]. However, to the best of our knowledge, few researches have been done for low-power structured ASICs although many power reduction techniques for standard cell designs are around. These techniques include multi-supply voltages, gate sizing, clocking gating, etc. for taming dynamic power and multi-threshold voltages, power gating, body-bias, gate length engineering, etc. for controlling leakage power. Taylor and Schmit [18] propose a VCLB architecture that employs dual supply voltages and gate sizing to reduce structured ASIC dynamic power. The VCLB is comprised of three stages. The first stage has three input buffers. Each buffer can be configured by vias into a level convertor. The second stage is a 3-input lookup table that can be configured to realize any three-variable logic function. The third stage is comprised of an output driver which can be configured into a driver of different drive classes. Although, this VCLB by itself can curtail dynamic power, it has not been used to create a cell library that can be employed by a logic synthesis tool to synthesize a circuit. Nevertheless, the above work has pioneered low-power structured ASIC. As transistor feature size continues to shrink, controlling leakage power is as important as curtailing dynamic power for many low-power applications. Hence, it is necessary to develop methodologies for controlling structured ASIC leakage power. Among leakage power reduction techniques [19-28], power gating [21-28] is one of the most effective methods. The main idea behind power-gating is to serially connect a high-Vth sleep transistor to a logic network and turn off the sleep transistor to reduce sub-threshold leakage current while the logic network is not active. Although this operation idea is simple, achieving optimal power-gating is very challenging [23]. The main problem is that it is hard to accurately assess the delay implication due to voltage drop across a sleep transistor. Hence, sleep transistors should be used under discretion. The voltage drop across a sleep transistor is a function of sleep transistor size and the current flowing through it. Given an amount of delay budget, sleep transistors are sized based on the current flow through it. Normally, we apply power gating only to the logic gates on non-critical paths. The objective is to maximize leakage reduction while minimizing sleep transistor size under delay budget. Sizing sleep transistors in a standard cell design is a difficult task [22]. It is even more challenging for structured ASICs due to transistors being prefabricated before logic and interconnect customization. In this paper, we apply power gating to structured ASICs for leakage power reduction. We present a power-gated via-configurable logic block (PGVCLB) and a power gated design flow mostly using existing standard cell design tools. The main features of PGVCLB and our contributions are as follows. z PGVCLB has a pair of equal-sized high-Vth pMOS devices which can be configured by vias into sleep transistors of different drive classes. This work is supported by National Science Council, Taiwan, under the grants NSC 96-2221-E-155-064-MY3 978-3-9810801-6-2/DATE10 © 2010 EDAA