HIGH GAIN AND PHASE MARGIN CMOS OPERATIONAL AMPLIFIER DESIGNS NEHA ARORA 1 , SHALU MALIK 2 , PRASHANT SINGH 3 & NARENDRA BAHADUR SINGH 4 4 Chief Scientist, MEMS, MS & RF ICS Design, Central Electronics Engineering Research Institute (CSIR-CEERI), Pilani, India 3 Senior Project Fellow at CSIR-CEERI, Pilani, India 1,2 M.Tech (VLSI Design) Trainees at CSIR-CEERI Pilani from Banasthali University, India ABSTRACT The paper presents the designs of high gain and phase margin low power cmos operational amplifiers near 200nm Technology, since it is a fundamental building block in all analogue integrated circuits. Up to the third order operational amplifier’s designs are presented in this paper, including the design of a fully differential folded cascode configuration with all the transistors are operating in saturation region in all configurations. The designs are carried out in parallel based on higher order model of operational amplifier and its circuit simulation in spice using Hspice model parameters. The mos transistor’s parameters’ optimizations were carried out to achieve the best performance of the operational amplifier near to 200nm Technology. The simulation results of the spice agree with the results of calculated parameters of the amplifier’s mathematical models. KEYWORDS: CMOS, OTA, Operational Amplifier, Analog Integrated Circuits INTRODUCTION The challenge in the design of op amps is the scaling down of the supply voltage and transistor channel length with each generation of CMOS technologies. As CMOS technology continues to evolve, the supply voltages are decreasing while at the same time, the transistor threshold voltages are remaining relatively constant. The decrease in the inherent gain of the nano-CMOS transistors is also of great concern. Traditional techniques for achieving high gain by vertically stacking (i.e. cascoding) transistors becomes less useful in sub-100nm processes. Horizontal cascading (multi-stage) must be used in order to realize op-amps in low supply voltage processes [3]. Obtaining high gain from an op-amp is of great importance. The first challenge in providing high gain is the small supply voltage which limits the cascade topology to have enough output voltage swing. Therefore the use of this topology in output stage is not suitable [4]. The second problem in the deep submicron process is small transistor’s output resistance. In order to increase this resistance one should decrease the bias current of transistor which in turn reduces the speed. Another solution to overcome to the problem is implementing gain boosting [5] to enhance gain in a high speed circuit. To achieve high gain, at least, two cascaded stages are required. Modern high performance analog integrated circuits make use of fully differential signal paths. Op-amps having differential input as well as differential output are referred to as fully differential op-amp. Common Feedback circuit is added with fully differential op-amp to provide the common mode output voltage [6]. THEORY Equivalent Circuit of a two stage operational amplifier is shown in figure 1. International Journal of Electrical and Electronics Engineering Research (IJEEER) ISSN 2250-155X Vol. 3, Issue 2, Jun 2013, 19-28 © TJPRC Pvt. Ltd.