Available online at http://www.idealibrary.com on doi:10.1006/spmi.1999.0809 Superlattices and Microstructures, Vol. 27, No. 2/3,2000 Series resistance limits for 0.05 μm MOSFETs P. KEYS † , H.-J. GOSSMANN, K. K. NG , C. S. RAFFERTY Bell Laboratories, Lucent Technologies, Murray Hill, New Jersey, U.S.A. (Received 9 November 1999) Technology scaling demands shallower junctions for MOSFETs, making high-conductivity access to the intrinsic device harder to achieve. Considerable effort has been devoted to improving process technology in order to reduce the sheet resistivity of shallow implanted layers. However, a calculation of the components of resistance as a function of technology node suggests that sheet resistance is unlikely to be a limiting factor in scaled MOSFETs. Contact and link-up resistance neighboring the channel will play an increasingly important part in driving junction technology. c  2000 Academic Press Key words: transistor, diffusion, resistance, scaling. 1. Introduction As transistor sizes are scaled down, there is increasing concern that series resistance may limit the ulti- mate performance of the scaled device: see, for example, Ref. [1]. At the same time as the intrinsic device resistance is decreasing with gate length, the shallower junctions necessary to minimize off-current give rise to increasing sheet resistivity in the source and drain. A large body of process research has been devoted to achieving minimal sheet resistivity and junction depth [2, 3], and considerable progress has been made using a combination of ultra low energy ion implantation and rapid thermal annealing. However sheet resistance is only one of several parasitic resistances in the access path to the device. This paper uses a combination of analytic and simulation estimates to analyze total resistance into its separate components, and examines them as a function of technology. 2. Transistor drive current To first order, the delay time of a digital switch can be written as C load V dd / I on where I on is the saturated drive current. The drive current has the interesting property of being essentially independent of technology generation, as shown in Fig. 1 [4]. Over a period of 5 years, when chip speeds have increased more than tenfold, the transistor drive current has remained essentially flat. This trend is expected to continue, according to the projections of the SIA roadmap [5]; the on-current is projected to be 750 mA µm −1 for NMOS and 350 mA µm −1 for PMOS at every node out to the end of the roadmap. † Current address: University of Florida at Gainesville. 0749–6036/00/020125 + 12 $35.00/0 c  2000 Academic Press