International Journal of Engineering and Technical Research (IJETR) ISSN: 2321-0869 (O) 2454-4698 (P) Volume-7, Issue-12, December 2017 123 www.erpublication.org Abstract— Due to the ever growing demand for high speed processors advancement in the technology regards to speed is the peak area of interest. The first word strike when the parameter speed is concerned is multiplication. Since multiplication is an important fundamental function in all mathematical computations it dominates the execution time of most throughput determination & CPU cycle time of a system. In a typical processor, Multiplication is one of the basic arithmetic operations and it requires substantially more hardware resources and processing time than addition and subtraction. In fact, 8.72% of all the instruction in typical processing units is multipliers. In computers, a typical central processing unit devotes a considerable amount of processing time in implementing arithmetic operations, particularly multiplication operations. In this project, the comparative study of different multipliers is done for low power requirement and high speed, also gives information of “Urdhva Tiryakbhyam” algorithm of Ancient Indian Vedic Mathematics which is utilized for multiplication to improve the speed, area parameters of multipliers. In this paper, we develop a novel architecture to perform high speed multiplication using ancient Vedic mathematics. One of the most efficient sutra in Vedic mathematics named as Urdhva Triyakbhyam strikes a difference in the actual multiplication process. In current scenario, the reversible logic design attracting more interest due to its low power consumption. Reversible logic is very important in low-power circuit design. The important reversible gates used for reversible logic synthesis are Feynman Gate, Fredkin gate, toffoli gate, New Gate sayem gate and peres gate etc. In this paper, evaluating various bits of reversible Vedic multiplier circuits based on Urdhava Triyakbhyam Sutras (Vertical and Crosswise Algorithm) to optimize the area, Quantum cost and garbage output of the Vedic multiplier circuits. This multiplier can be efficiently adopted in designing Fast Fourier Transforms (FFTs) Filters and other applications of DSP like imaging, software defined radios, wireless communications. The Total Reversible Logic Implementation Cost (TRLIC) is used as an aid to evaluate the proposed design. The proposed algorithm is developed using Verilog HDL. Implementation has been done using Xilinx14.6. Index Terms— Quantum Computing, Reversible Logic Gate, Vedic Mathematics, Urdhava Triyakbhyam, Optimized Design, Total Reversible Logic Implementation Cost (TRLIC) I. INTRODUCTION With the advancement in the VLSI technology, there is an ever increasing quench for portable and embedded Digital Signal Processing (DSP) systems. DSP is omnipresent in almost every engineering discipline. Faster additions and multiplications are the order of the day. Multiplication is the Naitik Pandya, M.Tech Scholar, Department of Electronics and Communication Faculty of Engineering, Pacific University Udaipur, India Sunil Sharma, Assistant Professor, Department of Electronics and Communication, Faculty of Engineering, Pacific University Udaipur, India Aabhas Mathur, Head & Associate Professor, Department of ECE, Aravali Institute of Technical Studies, Udaipur most basic and frequently used operations in a CPU. Multiplication is an operation of scaling one number by another. Multiplication operations also form the basis for other complex operations such as convolution, Discrete Fourier Transform, Fast Fourier Transforms, etc. With ever increasing need for faster clock frequency it becomes imperative to have faster arithmetic unit. Therefore, DSP engineers are constantly looking for new algorithms and hardware to implement them. Vedic mathematics can be aptly employed here to perform multiplication. Vedic Mathematics is one of the most ancient methodologies used by the Aryans in order to perform mathematical calculations. This consists of algorithms that can boil down large arithmetic operations to simple mind calculations. The above said advantage stems from the fact that Vedic mathematics approach is totally different and considered very close to the way a human mind works. The efforts put by Jagadguru Swami Sri Bharati Krishna Tirtha Maharaja to introduce Vedic Mathematics to the commoners as well as streamline Vedic Algorithms into 16 categories or Sutras needs to be acknowledged and appreciated. The Urdhva Tiryakbhayam is one such multiplication algorithm which is well known for its efficiency in reducing the calculations involved. Another important area which any DSP engineer has to concentrate is the power dissipation, the first one being speed. There is always a tradeoff between the power dissipated and speed of operation. The reversible computation is one such field that assures zero power dissipation. Thus during the design of any reversible circuit the delay is the only criteria that has to be taken care of. In a reversible Urdhva Tiryakbhayam Multiplier had been proposed. The proposed multipliers are designed using Vedic mathematics and the evaluation of these multipliers having different bits by the use of reversible logic gates to optimize the area, Quantum cost and garbage output of the multipliers. The methodology started with the conventional logic design implementation of a 2x2 Urdhva Tiryakbhayam multiplier using the irreversible logic gates. In the four expressions for the output bits are derived and are used to obtain the reversible implementation. The overall performance of the UT multiplier is scaled up by optimizing each individual unit in terms of quantum cost, garbage outputs etc. The design expressions can be logically modified so as to optimize the design. The reversible logic circuit with multiple numbers of same inputs is not advisable. Finally the designed structure is simulated and the result is obtained which gives the report objective. II. VEDIC MATHEMATICS Vedic Mathematics is the name given to the ancient system of Indian Mathematics which was rediscovered from the Vedas between 1911 and 1918 by Sri Bharati Krishna Tirthaji (1884-1960). According to his research all of mathematics is Evaluation of Reversible Computing Using Ancient Methods Naitik Pandya, Sunil Sharma, Aabhas Mathur