EMPC 2013, September 9 - 12, Grenoble; France Silicon interposers with Integrated Passive Devices, an excellent alternative to discrete components. Florent LALLEMAND, Frédéric VOIRON IPDIA, 2 rue de la girafe, Caen, FRANCE Phone: +33(0)760934532 florent.lallemand@ipdia.com Abstract A new way of designing high density silicon capacitors that are intended to be co-integrated with TSV for advanced silicon interposers is presented. This new kind of design; called “mosaic” enables to manufacture IPDs with capacitor density up to 500nF/mm² while maintaining ultra low ESR. PICS™ “mosaic” capacitors implement localized elements set in parallel on a grid that behave as a parallel network and exhibit the following characteristics:  The global “mosaic” capacitor has a linear dependency with C Global =N*C Local where N is the number of repetitions of the localized element and C Local its capacitance  ESR and ESL have an inverse dependency with N : L Global =L Local /N and ESR Global =ESR Local /N.  Thanks to the 1/N variation of both ESL and ESR; and the N/1 variation of C respectively, the products ESR*C and ESL*C are nearly constant which respectively means that the cutoff and SRF of the device are also constant, whatever the N value is. The global capacitor performances (like SRF) are driven by the most elementary building block and almost independent from the capacitor size Key words: silicon interposer, integrated passive devices, high density silicon capacitor, ultra low ESR, PICS™ technologies. Introduction IPDIA is one of the key players in the integrated passive devices manufacturing. Thanks to its proprietary Passive Integration Connective Substrate (PICS™) technology range, passive components such as capacitor, resistors, inductors, diodes (…) can be integrated onto silicon with a minimal footprint and without any tradeoff on the device performances [1]. Among these passive components, high density 3D capacitors make up the beating heart of the PICS™ technologies: the combination of patented [2] high aspect-ratio micrometric 3D structures (50:1 pores or trenches, drilled in the silicon by Deep Silicon Reactive Ion Etching, see Figure 1) with standard low-k (silicon oxide and/or nitride) from the semiconductor industry in single (or multiple) Metal Insulator Metal (MIM) architectures (Figure 2) enables the process of devices up to 250 nF/mm². Figure 1: SEM micrographs example of the high aspect- ratio structures etched in the silicon substrate (pores of AR ~ 17:1 on the left, tripods of AR~50:1 on the right) Such a capacitor density is reached with the production proof process called PICS3™ currently used to provide high-end capacitors for many applications, like pacemakers, enabling in this former case, a significant size reduction of the implantable device and thus, a lower invasive surgery. Figure 2: On the left: cross sectional view of the MIMIM architecture used in the PICS3 technology. On the right: the schematic (voluntary simplified) showing how the capacitors are parallelized in a MIMIM architecture to offer a higher capacitance value than in single MIM IPDIA PICS™ technologies These 3D silicon capacitors based on the various PICS™ processes from IPDIA exhibit outstanding performances such as:  Capacitance density up to 250 nF/mm² with breakdown voltage (V BD ) of 11V minimum  « Intrinsic lifetime » t 0.1% > 10 years @ 3.6V, 100°C (60% C.I.) even for corner batches  Low leakage for low power consumption (typically < 5 nA/µF and down to < 0.2 nA/µF @ 3.2V/25°C) (a) 50μm 2 μm (a) (b) 17μm 2 μm Low Ohmic substrate P+, 20 mOhm.cm Top electrode (in-situ doped Polysilicon2) Passivation layer (SiO 2 ) N++ Area Silicon substrate Middle electrode (in-situ doped Polysilicon1) Dielectric1 Polysilicon1 Dielectric2 Polysilicon2 Bottom electrode (N++ area) Polysilicon 1 (PS1) Metal layers Metal layers PS1 PS1 PS2 N++ Dielectric 2 Dielectric 1 Simplified MIMIM architecture from the PICS3™ Related schematic