IOSR Journal of Electronics and Communication Engineering (IOSR-JECE) e-ISSN: 2278-2834,p- ISSN: 2278-8735. PP 01-11 www.iosrjournals.org National Conference on Mechatronics, Computing & Signal Processing(MCSP 2016) 1 | Page FPGA implementation of Angle Generator for CORDIC Based High pass FIR Filter Design Nutan Das 1 , Swarnaprabha Jena 2 , Siba Kumar Panda 2 1 M.Tech Scholar,VLSI Design, Centurion University of Technology & Management, BBSR, Odisha 2 Assistant Professor, Department of ECE, Centurion University of Technology & Management, BBSR, Odisha Abstract: The design of high speed VLSI architecture introduced a large number of algorithmes for real-time Digital Signal Processing(DSP) and in the VLSI Technology, the realizations of this DSP algorithmes have been directed in many of the computations in Signal Processing and wireless communication appilications such as trigonometic and complex functions. This paper proposed a hardware efficient CORDIC based parallel architechture for the calculation of cosine and sine functions and High Pass FIR (Finite Impulse Response )Filter design using Very High Speed Integrated Circuit Hardware Description Language (VHDL). The generation of cosine sine functions of CORDIC algorithm have synthesized, simulated and tested it on Xilinx FPGA SPARTAN 3E kit.The code have synthesized using Xilinx ISim 14.4 simulator software. This paper also described the angle to 15bit binary conversion, analysis of all output values and the power utilization summary .Finally, magnitude plot of HighPass FIR Filter is plotted and analysed. Keywords: CORDIC, FPGA, FIR FILTER, SIGNAL PROCESSING, VLSI SIGNAL PROCESSING, VHDL I. Introduction In advanced VLSI technology have stimulated a great interest in developing special purpose processor architecture arrays to facilitate real-time signal processing. The reductions in the hardware cost, less area, high speed and less power consumption are motivated the development of various architectures to design filters in Digital Signal Processing. Generally, DSP algorithms use the calculation of elementary functions which require high computational power. Now, Field-Programmable Gate Array (FPGA) is introduced hardware technology for DSP systems offer the capability to develop the most suitable architecture for the computational, memory and power requirements of the DSP applications. For FPGA implementation the DSP system produced highly parallel, pipelined and hybrid architecture. These Filters are used to demonstrate the mapping, introduced retiming and the low power optimizations are demonstrated by using a FFT-based applications and development. In the CORDIC(Coordinate Rotation Digital Computer), J.E. Volder [1], Rotation is a 2-D( dimensional) vector and a target angle is divided into desired rotation angle into the weighted sum of a set of predefined elementary rotation angles in which through each rotation can be realized with shift and add/sub operations. Also, the CORDIC algorithm is again extended [2] to proposed a unified algorithm for computation of rotation in and hyperbolic coordinate systems, circular, linear, embedding coordinate system. These functions are implemented for many applications like digital signal processing [3]. CORDIC used mainly simple shift and add operations[4], that performed several computational tasks are calculation of trigonometric functions(cosine,sine), hyperbolic functions(htan,hcos) and logarithmic functions, real and complex functions, and simple arithmetic functions are multiplications, division, square-root functions Now CORDIC Algorithms are used in the area of signal and image processing and communication systems, robotics and 3-D(Dimensional) graphics, Fast Fourier Transforms(FFT), Filters, Computer Graphics[5] and Robotics [6]. CORDIC offers high computational applications: computer graphics, in which a combination of scaling and rotations are required for real time world. For fast computation programming CORDIC is again used in the field of Robotics. II. Background And Literature Review Amritakar Mandal etal. [7] described the design of pipelined architecture for the computation of Sine and Cosine values and it is based on application of a specific CORDIC processor. The design of CORDIC is mainly based on the circular rotation mode gives a high system throughput by reducing latency in each individual pipelined stage. Lakshmi.B etal. [8] explained a low latency field programmable gate array implementation of an unfolded architecture for the implementation of rotational CORDIC algorithm. Here the computational device was highly suitable for the implementation of customized hardware in portable devices and in which a large parallelism and low clock rate were utilized for low power consumption.