JOURNAL OF ELECTRONIC TESTING: Theory and Applications, 1, 229-234 (1990) 9 1990 Kluwer Academic Publishers, Boston. Manufactured in The Netherlands. Exact Probabilistic Testability Measures for Multi-Output Circuits E CAMURATI, E PRINETTO, AND M. SONZA REORDA Politecnico di Torino, Dipartimento di Automatica e Informatica, Corso Duca degli Abruzzi 24, 1-10129 Turin, Italy Received July 27, 1989. Revised May 4, 1990 and May 18, 1990. Abstract. The computation of probabilistic testability measures has become increasingly important and some methods have been proposed, although the exact solution of the problem is NP-hard. An exact analytical method for single- output combinational circuits is extended to deal with multi-output circuits. Such circuits are reduced to single- output ones by introducing a dummy gate, the "X-gate," and applying to the resulting graph the analysis based on supergates. Key words: Built-in self-test, CAD tools, probabilistic testability analysis, test-pattern generation. 1. Introduction The past years have witnessed an increasing use of probabilistic testability measures, and many algorithms are known from the literature [1, 2, 3]. Their common denominator is reliance on approximations. An experi- mental comparison of some of the most popular ones is presented in [4]. Although the exact computation of fault-detection probabilities is an inherently NP-hard problem, some methods are available for its solutions: 9 exhaustive fault simulation, whose complexity is 0(2 n) in the number of primary inputs (PI) 9 Boolean differences [5], first finding the detectability function for each fault and then the number of input combinations that satisfy it. Both processes have ex- ponential complexity [6] 9 analytical methods such as [7], [8], or [9], based on "supergates" and with complexity of (9(2 m) (m < n). Monte Carlo simulation has been advocated as a possible compromise between accuracy and computa- tional cost, but it has been shown that the problem is #-complete [10] if one requires an error less than a max- imum e with a probability greater than a threshold 6. Here, we extend the method of [9] and [11], originally limited to single-output combinational circuits, to multi- output circuits. Section 2 recalls the method, section 3 presents the extension to multi-output circuits. Exam- ples and experimental data support the conclusions. 2. Single-Output Combinational Circuits In order to make this presentation self-contained, this section summarizes how the analytical method of [9] and [11] works to yield exact testability measures for single-output combinational circuits. A previous paper [12] formally states the problem in terms of probability theory. The method of [9] and [11] is based on a graph ap- proach, where the circuit is partitioned according to signal independence criteria. The subcircuit associated to a generic line l is called "supergate" [2] and repre- sents the minimum set of predecessors of l such that the inputs (~ to the subcircuit are independent, that is, they depend on disjoint subsets of PIs. There are two kinds of inputs to the supergate: fan-out inputs (FI) and non-fan-out inputs (NFI). FIs are such that there is more than one path leading from the FI to the output of the supergate. The basic idea is to enumerate within a supergate the 2 card(FO combinations on the FIs and to compute condi- tional probabilities for each of them. Total probability is obtained by multiplying each conditional probability by the probability of occurrence of the combination on the FIs and adding them up. Given a line l which is the output of a gate in the supergate, denoting as C 1its controllability to value 1 and as C I its conditional controllability to value 1 when the combination A i is applied to the FIs, the fol- lowing formula holds: