Design and Implementation of High Speed Multiplier based on Vedic Mathematics: A Review {tag} {/tag} International Journal of Computer Applications Foundation of Computer Science (FCS), NY, USA Volume 155 - Number 8 Year of Publication: 2016 Authors: Pramod S. Aswale, Priyanka Nirgude, Bhakti Patil, Rohini Chaudhari 10.5120/ijca2016912385 {bibtex}2016912385.bib{/bibtex} Abstract Multipliers being the key components of various applications and the throughput of applications depends on Arithmetic and logic units(ALU), Digital signal processing blocks and Multiplier and accumulate units. Vedic Multiplier has become highly popular as a faster method for computation and analysis.So that the latency of conventional multiplier can be reduced. Here the vedic mathematic Sutra- ‘Urdhva Tiryagbhyam’ and Nikhilum are used for efficient multiplication. The main parameters for improvement are speed, delay, hardware complexity. From this review, the conclusion regarding how well a challenge has been solved, and recognize prospective research areas that require auxiliary effort. References 1. G.Ganesh Kumar, V.Charishma , “Design of High Speed Vedic Multiplier using Vedic Mathematics Techniques” International Journal of Scientific and Research Publications, Volume 1 / 4