Understanding the mobility reduction in MOSFETs featuring high-κ dielectrics P. Toniutti, M. De Michielis, P. Palestri, F. Driussi, D. Esseni and L. Selmi DIEGM, University of Udine- IU.NET, Via delle Scienze 208, 33100, Udine, Italy, paolo.toniutti@uniud.it Abstract In this paper we analyze by means of accurate Multi- Subband Monte Carlo simulations the mobility reduc- tion associated to high-κ dielectrics in a large number of n- and p-MOSFETs. We argue that soft optical phonon scattering can not explain the experimental mobility re- duction for neither the electron nor the hole inversion layer. In order to reproduce the experimental data, a large amount of Coulomb centers in the gate stack is re- quired, which would result in a huge threshold voltage shift not observed in the experiments. Even if we as- sume the remote charge to be in the form of dipoles, the associated threshold voltage shift is still large and not consistent with the experimental findings. 1. Introduction The scaling process implies the reduction of the equivalent oxide thickness (EOT) to improve electro- static integrity and to limit short channel effects. If pure SiO 2 is used, oxide thickness below 1 nm is needed in high performance devices scheduled in production for the year 2010 [1]. This results in an excessive gate leak- age current due to electron tunneling across the dielec- tric [2]. High-κ (HK) dielectrics can relax this problem since they provide the same EOT with a thicker layer compared to their SiO 2 counterpart. Unfortunately, gate stacks featuring HK dielectrics have consistently shown a lower mobility with respect to the well known univer- sal curves. The problem is somewhat alleviated by the introduction of an interfacial SiO 2 layer (ITL) between the channel (Si) and the HK material. Several mechanisms have been invoked to explain this mobility degradation. Soft optical phonons (SOph) have been considered the main responsible for long time, based on the model in [3]. However, more re- cent studies predict a significantly weaker influence of SOph on the electron mobility [4–6]. Coulomb centers in the the gate stack (remQ) have also been proposed as a possible cause for the mobility reduction [7], but very large charge densities are necessary to justify the exper- imental mobility degradation [4]. These charges would produce a large flat-band voltage shift inconsistent with the experiments. Recent experimental data and atomistic simulations suggest that the mobility degradation could be due to interface dipoles close to the HK/ITL interface (DipQ) Si ! ! HK + ! + ! + ! 0 z HK t ITL t metal gate Si channel D dip d A B C S high!k dielectric interfacial layer q 1 ITL ! q 2 Fig. 1. Sketch of the gate stack structure considered in this work. The possible locations of the interface dipole are also shown. [8–10]. In the simulation area a large number of models has been proposed which provide quite a broad spec- trum of predictions [4, 11], making the global scenario still unclear. In this paper we examine the effect of the soft optical phonons, remote Coulomb scattering and interface dipoles on the n- and p-MOSFET mobility. 2. Models We use established Multi Sub-band Monte Carlo (MSMC) models to perform the mobility calculations for electron and hole inversion layers: the model for the n-MOSFET is based on the effective mass approxima- tion [12], whereas the one for the p-MOSFET [13] is based on the analytical model presented in [14]. In the following, we briefly describe the models im- plemented to simulate devices with a gate stack featur- ing an HK sandwiched between an ITL and a metal gate (see Fig. 1). All interfaces are assumed to be abrupt. A. SOph and remQ scattering The SOph and RemQ scattering models for n-MOS are described in [4]. For the p-MOS case, they have been extended using the same formulation for the ma- trix element, but computing the scattering rate accord- ing to the analytical band structure for hole inversion layers in [14]. B. Modelling of the DipQ scattering On the same grounds as the remQ model [15], the scattering potential due to dipoles oriented perpendic- ularly to the ITL/HK interface (see Fig. 1) is obtained ULIS 2010 - Ultimate Integration on Silicon University of Glasgow, 18-19 March 2010 65