Area and Power Efficient 2 Bit Multiplier by Using Enhanced Half Adder Akshay Kamboj, Manisha Bharti, and Ashima Sharma Abstract In this paper, a novel design of half adder (HA) is proposed using low power and area-efficient XOR and AND gates. Multipliers are essential component mostly used arithmetic unit. Using novel HA, novel design of multiplier and its area utilization is discussed along with conventional design. The performance of proposed circuit is analyzed using Cadence Virtuoso on 90-nm Generic Process Design Kit (gpdk) Complementary Metal Oxide Semiconductor (CMOS) technology at 1 V supply voltage (V dd ) at maximum of 50 GHz frequency. Compact high-performance systems require consolidated high-speed multipliers. The simulated result indicates that the proposed multiplier utilizes 33.79% lower area as compared to conventional method. A low power 2 bit multiplier based on the novel full swing half adder (HA) also shows lower power consumption by 12.42% over conventional multiplier. Keywords Half adder (HA) · Multiplier · Generic process design kit (gpdk) · Complementary metal oxide semiconductor (CMOS) 1 Introduction Over last few decades, the demand for more functionality and high performance for portable systems has increased drastically which has drawn the consent to increase the compactness of the portable systems. Area and power efficiency are important requirements in high-speed interface circuit [1]. Many research efforts are required to provide enhancement in these parameters. There are various elementary as well as composite ways to implement multiplier containing multiple digital circuits. The rendition of the multiplier can be enhanced by improvement in any fundamental structural block [2]. A 2 bit conventional multiplier contains 4 NAND gates and 2 half adder. Further, the HA contains XOR and AND A. Kamboj (B ) · M. Bharti · A. Sharma Department of Electronic and Communication Engineering, National Institute of Technology Delhi, New Delhi, India e-mail: nishukamboj95@gmail.com © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2021 P. K. Singh et al. (eds.), Evolving Technologies for Computing, Communication and Smart World, Lecture Notes in Electrical Engineering 694, https://doi.org/10.1007/978-981-15-7804-5_27 361