RECENT ADVANCES IN ELECTRONICS AND COMMUNICATION ENGINEERING-2017(RAECE-2017) @IJRTER-2017, All Rights Reserved 531 High Speed Level Shifters for Low Power Applications with Reduced Size Priyanka Boshetty Department of Electronics and Communications Engg. NNRG College of Engineering, Hyderabad, India Umadevi Gurram Department of Electronics and Communications Engg. NNRG College of Engineering, Hyderabad, India Srinivas Reddy Panati Department of Electronics and Communications Engg. NNRG College of Engineering, Hyderabad, India Abstract — In this paper a high speed level shifter is proposed for low power applications. This circuit is a power efficient level shifter that converts low level input voltages to high level voltages as per the design requirement. The efficiency of pull up and pull down transistors are improved in the proposed method and the circuit was tested by using 180 nm CMOS technology. A unit buffer and inverter circuit was introduced to the load circuits and input buffers to have fair comparison between different structures. The overall power consumption in the proposed circuit was reduced to a minimum level by reducing the number of transistors to build a level shifter. Keywords—Level Shifter, Low Power, Source Follower, CMOS Technology. I. INTRODUCTION In day to day life, there is a need of increase in handheld devices like mobile phones, cameras, speakers etc. With the increase in these portable devices, low power consumption has become an important issue in integrated circuits. The heat dissipation caused by enormous power consumption creates a problem that badly effect the reliability, efficiency and cost of the system design. In order to develop techniques for minimizing power dissipation, it is essential to identify various sources of power dissipation and different parameters involved in each of them. The total power for a VLSI circuit consists of dynamic power and static power. In (SoC) design, different components are fabricated on a single chip and needs different voltages to obtain optimum performance. In modern VLSI system circuits, the design of level shifters using multiple supply voltages has been widely used. Multi Supply Voltage Domain (MSVD) technique is an effective method to reduce dynamic, static and leakage Power in modern system-on-chips. Dynamic power results due to switching of load capacitance between two different voltage logic levels. Static power is caused due to short circuit paths between the supply voltage and ground. Leakage power results in leakage currents that arise from substrate injection and sub-threshold [7]. Level shifters are used as an interface between different voltage domains. In multi supply voltage system design, a level shifter is used to convert from voltage level to another voltage level. Conventional level shifter is capable of handling low voltage input and shifts any voltage level to a desired voltage level [1]. A low voltage signal may not have threshold value more than that of high voltage signal. Therefore, a level shifter is used to interface between two different voltage domains. A Conventional level shifter consists of a cross coupled PMOS and NMOS driven by an input signal. When low voltage circuit drives high voltage circuit the PMOS of high voltage domain does not turn off completely by low voltage circuit. As a result, it leads to increase in leakage currents and power consumption. Hence level shifters are used to reduce unwanted power consumption. Fig. 1. Basic block diagram of level Shifter A. Level Shifter Due to advancement in VLSI technology, leads to complex circuits resulting in increase in functionality and power dissipation. Energy Efficiency is a primary concern in modern CMOS circuits. The major sources of power dissipation are static and dynamic power. Static power is mainly due to leakage currents, whereas dynamic power is due to supply voltages and charging and discharging of load capacitance [5]. The dynamic energy is directly proportional to supply voltage. Low supply voltage results in decreasing in dynamic power quadratically [6]. That is, higher the supply voltage higher the energy consumption. In order to reduce the dynamic power consumption without degrading the performance of the circuit level shifters are used. For analog and mixed signal circuits level shifter plays a crucial role. The low power level shifter circuit consists of three stages input stage, level shifter or level converter, output stage. The main objective of each level shifter is to reduce power dissipation, reduce chip size, area and to decrease the cost of integrated circuits. Fig. 2. Level Shifter circuit There are two types of level shifters:  Single supply level shifter (SSLS)  Dual supply level shifter (DSLS)