Designing series of fractional-order elements Jaroslav Koton 1 • Jan Dvorak 1 • David Kubanek 1 • Norbert Herencsar 1 Received: 17 February 2020 / Revised: 5 February 2021 / Accepted: 13 February 2021 / Published online: 8 March 2021 Ó The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2021 Abstract In this paper we propose an efficient approach to design fractional-order elements’ (FOEs) series, while using a very limited set of ‘‘seed’’ FOEs. The proposed approach follows the idea of general immittance inverter/converter, whereas a suitable circuit solution employing operational transconductance amplifiers is also presented and can be used for the design of grounded FOEs with the fractional order a being in the range ½2; 2. The proposed circuit may simply be extended to design fractional-order elements from wider range of a to follow designers’ requirements. To show the efficiency of the described technique, the use of only up to two ‘‘seed’’ FOEs with properly selected fractional order a seed as passive elements results in the design of a series of 17 FOEs with different a being in the range ½2; 2. Cadence post-layout simulation results are presented that prove operability and robustness of our design concept. Basic fractional 1.75-order low-pass filter is also presented to show the utilization of a FOE being implemented by the proposed GIC. Keywords Fractional-order element  Transformation  Immittance inverter/converter  OTA 1 Introduction During the last few decades, fractional-order calculus gained significant attention in various engineering areas, as e.g. in control or modelling it provides beneficial properties compared to classic integer-order systems [6, 22]. The efficient utilization of fractional-order calculus and systems may also be observed in agriculture [27], biology [9], electrical engineering [4] or cryptography [28]. Dealing signal processing, controller, or generally analogue func- tion block design, the fractional-order element (FOE) as discrete element (together with other passive and active elements) becomes essential for the implementation of the required circuit solution. However, the presence of FOE as readily available discrete element is not common yet. In [20] a comprehensive survey of recent progress and pos- sible design techniques and approaches to implement FOEs of capacitive type are described, but all of them are still at the stage of laboratory experiments and samples used by the individual research groups. Therefore, to design and mainly evaluate the performance of fractional-order sys- tems, the required FOEs (capacitive-type) are nowadays suitably emulated by RC networks, like Foster, Cauer or Valsa topologies [5, 12, 16, 18, 26]. In [25], a systematic procedure for designing Foster-I, Foster-II, Cauer-I and Cauer-II RC networks, which approximate the capacitive FOE with generally any values of its parameters (i.e. the pseudo-capacitance C a and the fractional-order a) in a required frequency range is pre- sented. However, the values of individual resistors and capacitors of the RC network must be precise to obtain the required accuracy of the approximation [25]. Requiring new values of C a and/or a also requires to determine new values of individual resistors and capacitors of the RC network. Additionally as also shown in [11], values of a being close to zero (0) or unity (1) results in very high ratio in values of resistors and capacitors in the RC network. As consequence, individual research groups dealing with fractional-order circuits design mostly use their & Jaroslav Koton koton@vut.cz Jan Dvorak dvorakjan@vut.cz David Kubanek kubanek@vut.cz Norbert Herencsar herencsn@vut.cz 1 Department of Telecommunications, Faculty of Electrical Engineering and Communication, Brno University of Technology, Technicka 12, 616 00 Brno, Czech Republic 123 Analog Integrated Circuits and Signal Processing (2021) 106:553–563 https://doi.org/10.1007/s10470-021-01811-4