1 Molecular beam epitaxy and defect structure of Ge (111)/epi-Gd 2 O 3 (111) /Si (111) heterostructures Krista R Khiangte 1 , Jaswant S Rathore 1 , Sudipta Das 2 , Ravinder S Pokharia 2 , Jan Schmidt 3 , H. J. Osten 3 Apurba Laha 2 , Suddhasatta Mahapatra 1 1 Department of Physics, Indian Institute of Technology Bombay, Mumbai, INDIA 2 Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, INDIA 3 Institute of Electronic Materials and Devices, Leibniz Universität Hannover, Schneiderberg 32, 30167 Hanover, Germany Abstract Molecular beam epitaxy of Ge (111) thin films on epitaxial-Gd 2 O 3 /Si(111) substrates is reported, along with a systematic investigation of the evolution of Ge growth, and structural defects in the grown epilayer. While Ge growth begins in the Volmer-Weber growth mode, the resultant islands coalesce within the first ~ 10 nm of growth, beyond which a smooth two-dimensional surface evolves. Coalescence of the initially formed islands results in formation of rotation and reflection microtwins, which constitute a volume fraction of less than 1 %. It is also observed that while the stacking sequence of the (111) planes in the Ge epilayer is similar to that of the Si substrate, the (111) planes of the Gd 2 O 3 epilayer are rotated by 180° about the [111] direction. In metal-semiconductor-metal schottky photodiodes fabricated with these all-epitaxial Ge-on-insulator (GeOI) samples, significant suppression of dark current is observed due to the presence of the Gd 2 O 3 epilayer. These results are promising for application of these GeOI structures as virtual substrates, or for realization of high-speed group-IV photonic components. I. INTRODUCTION The germanium (Ge)-on-insulator (GeOI) technology is rapidly emerging as an enabling platform for a variety of applications in microelectronics, photonics, and photovoltaics. As the silicon (Si) microelectronics industry encounters technological and economic challenges to enhance speed and reduce power consumption, while minimizing the footprint of the field-effect transistors on microprocessor chips, mobility enhancement approaches are being aggressively pursued to meet performance requirements of the sub-22-nm technology node. In this context, GeOI is attracting tremendous attention as an engineered material system with high carrier mobilities, while harnessing the “on-insulator” advantages [1-4]. Besides, GeOI substrates are mechanically more stable and less expensive than those of bulk Ge, thus providing a practical advantage in device processing.