PCB drop test lifetime assessment based on simulations and cyclic bend tests P.F. Fuchs a,⇑ , G. Pinter a,b , Z. Major c a Polymer Competence Center Leoben GmbH, Roseggerstrasse 12, 8700 Leoben, Austria b Material Science and Testing of Plastics, Department Polymer Engineering and Science, University of Leoben, Otto Gloeckel-Strasse 2, 8700 Leoben, Austria c Institute of Polymer Product Engineering, Johannes Kepler University Linz, 4040 Linz, Austria article info Article history: Received 14 May 2012 Received in revised form 2 November 2012 Accepted 2 January 2013 Available online 11 February 2013 abstract The aim of this work was to predict the performance of printed circuit boards (PCBs) in a board level drop test (BLDT). The applied methodology was based on results of a board level cyclic bend test (BLCBT) and an according finite element simulation of the test. A function, describing the relation between a local loading parameter, determined in the simulation model for different deflection amplitudes of the BLCBT, and the according cycles to failure, measured in the experiments, was modelled. The method was eval- uated by comparing the predicted results of two additional PCB built-ups with experimentally deter- mined lifetimes. The determined lifetimes agreed very well, although the differences between the analysed PCB types were not very clear. Applying the known correlation between the BLCBT and the BLDT, the predicted results for the BLCBT could be used to estimate the BLDT performance. Ó 2013 Elsevier Ltd. All rights reserved. 1. Introduction Printed circuit boards (PCBs) are the linking part in all electronic devices. They bring together all applied components and connect them through a complex structure of conducting paths. They are used in almost every product, including electronic systems. Nowadays mobile devices represent one major area of application of rising interest. Related research is focused on small, high perfor- mance gadgets with an increasing number of features. Thus, the PCB industry faces some demanding challenges. Multilayer boards with multiple thinner layers (boards with up to 22 layers are state of the art), lower conducting path sizes and smaller via diameters are increasingly sought after. These developments are counteract- ing the effort of ensuring the reliability of the devices and necessi- tate an optimized design, based on improved understanding of material behaviour. The range of loads, PCB have to endure during their lifetime is – due to their large field of applications – wide spread. E.g. for mobile devices, impact loads are of special interest, as they are especially prone to be dropped. These impact loads are considered within this work. The current industry-wide standard to evaluate the drop performance of PCB is a board level drop test (BLDT) [1]. Thereby, an instrumented drop of a defined test board is repeated, till a fail- ure is detected. The number of drops till failure is used as an indi- cator for the drop test reliability. An accelerated test, a board level cyclic bend test (BLCBT) [2], applying a sinusoidal load continu- ously, has been developed as an alternative. The advantage of this method, next to shorter testing times, is very precisely defined boundary conditions, compared to those used in a BLDT test. This simplifies the finite element (FE) simulation of the experiment, which is crucial for the presented approach. However, the experimental methods exhibit the drawback of being both time consuming and expensive. PCB producers have to design, produce, assemble (has often to be done externally) and repeatedly test (to achieve a relevant statistical statement) the PCB. Between design completion and a first reliability estima- tion, there are rather long waiting times. Therefore, there is an ef- fort to accelerate the reliability and lifetime estimation by performing FE simulations. The prediction of both the global and local deformation and damage behaviour has been tried in several works (e.g. [3–8]); moreover, attempted to be set in correlation with the PCB reliability. So far, several promising results and com- plimentary correlations between simulation results and experi- mentally observed lifetimes were established and presented. However, in order to accurately describe a correlation between the simulation results and the fatigue lifetime, a number of differ- ent board designs, covering a representative range of the PCB life- times, had to be analysed in the BLDT. Here, a method, allowing the generation of a correlation curve by testing just one PCB design, is presented. The predominant number of failures in PCB during a BLDT or BLCBT is allocated at or near the vicinity of the solder bumps, con- necting the board with the mounted components. Typical failure patterns are depicted in Fig. 1. The failures initiate either in the insulation, the solder ball or at the interface and grow through the solder ball or the copper via and thus result in an electrical dis- continuity. These discontinuities are identified as failure when they once exceed 1000 X during the experiments. The failure type depends on the PCB built-up and design. 0026-2714/$ - see front matter Ó 2013 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.microrel.2013.01.001 ⇑ Corresponding author. E-mail address: peter.fuchs@pccl.at (P.F. Fuchs). Microelectronics Reliability 53 (2013) 774–781 Contents lists available at SciVerse ScienceDirect Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel