On Three-Dimensional Layout of Interconnection Networks (Extended Abstract) * Tiziana Calamoneri 1 and Annalisa Massini -~ Dipartimento di Matematica and Dipartimento di Scienze dell'Infbrmazione, Universit£ di Roma "La Sapienza', Italy - calamo@dsi.uniromal.it. 2 Dipartimento di Scienze dell'Informazione, Universit£ di Roma "La Sapienza", Italy - massini@dsi.uniromal.it. Abstract. In this paper we deal with the layout of interconnection net- works on three-dimensional grids. In particular, in the first, part we prove a general formula for calculating an exact value for the lower bound on the volume. Then we introduce the new notion of k-3D double channel routing and we use it to exhibit an optimal three-dimensional layout for butterfly networks. Finally, we show a method to lay out multig~d and X-tree networks in optimal volume. 1 Introduction and Preliminaries Recent hardware advances have allowed three-dimensionM circuits to have a cost low enough to make them commonly available. For this reason three-dimensional layouts of graphs on rectilinear grids are becoming of wide interest both in the study of the VLSI layout problem for integrated circuits and in the study of algorithms for drawing graphs. Indeed, the tie between VLSI layout studies and theoretical graph drawing is very strong since to lay out a network on a grid is equivalent to orthogonally draw the underlying graph. To the best of our knowledge, not many papers have been written about three-dimensional grid drawing of graphs [2, 3, 4, 5, 6, 10] and all of them show results that are valid for very general graphs and therefore they do not work efficiently for structured and regular graphs such as the most commonly used interconnection networks. On the other hand, the importance of representing interconnection networks in three dimensions has already been stated in the 80's by Rosenberg [12]: the most relevant aims are to shorten wires and to save in material. By virtue of the equivalence between 1Gvout of networks and drawing of graphs in the following we will prefer the network terminology instead of the graph theory one; therefore we will use the word 'node' instead of ~verte×' and 'layout' instead of 'drawing', while we will interchangeably use the terms 'graph' and 'network', 'edge' and 'wire'. In this paper we focus our attention on three-dimensional grid layout of an interconnection network ~, that is a mapping of 6 in the three-dimensional grid * The first author has been supported by Italian National Research Council.