Research Article Low-Cost Fault Tolerant Methodology for Real Time MPSoC Based Embedded System Mohsin Amin, Muhammad Shakir, Aqib Javed, Muhammad Hassan, and Syed Ali Raza Department of Electrical Engineering, COMSATS Institute of Information and Technology, Abbottabad, Pakistan Correspondence should be addressed to Mohsin Amin; mohsinamin@hotmail.com Received 28 July 2014; Revised 27 October 2014; Accepted 27 October 2014; Published 19 November 2014 Academic Editor: Nadia Nedjah Copyright © 2014 Mohsin Amin et al. Tis is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. We are proposing a design methodology for a fault tolerant homogeneous MPSoC having additional design objectives that include low hardware overhead and performance. We have implemented three diferent FT methodologies on MPSoCs and compared them against the defned constraints. Te comparison of these FT methodologies is carried out by modelling their architectures in VHDL-RTL, on Spartan 3 FPGA. Te results obtained through simulations helped us to identify the most relevant scheme in terms of the given design constraints. 1. Introduction Tere has always been an urge of high performance; subse- quent to this, plenty of eforts have been made to attain higher levels in said aspect. In past, technology scaling was mainly used for performance improvement. Tis approach was quite helpful in handling various applications with high processing demands; however bottleneck of this approach has been reached now [1]. Continuous transistor scaling resulted in reduced nodal capacitances and low supply voltages making the devices more prone to the transient faults caused by external (alpha particles and neutrons) and internal (power supply noise and cross talk noise) noises [2]. Transient faults are more likely to occur than permanent faults [3]; that is, product monitoring shows that permanent faults rate as a result of external events is not more than 10 FIT (failure in time) whereas the transient fault rate of 1 Mbit of SRAM is around 1,000 FIT for modern process technologies. Tus transient faults have major part in disturbing the reliability of the system [4]. Methods such as rollback are considered efective in rectifying transient errors. However in hard real time systems such corrections have a huge infuence on the response time of the system. A deadline miss in the task can result in the failure of the system [5]. For example, ATM machines, cell phones, and thumbprint scanners are some real time systems. In last decade, to address high performance need there has been a shif towards multiple resource system. Diferent interconnect structures have been employed in such systems including point to point (P2P) and bus based [6]. Both these architectures were quite useful until we had only few processors connected through them but as the number of processing elements (P.E) increased several issues were spotted and P2P has limited scalability due to increased complexity [7] while, in buses, scalability is restrained due to the fact that by raising the number of processing elements the resulting propagation delay increases [8]. Bus based architecture can be implemented conveniently if number of processors are less than fve [9]. To overcome the defciencies of the above mentioned interconnect structures network on chip (NoC) communi- cation architecture has been adopted. Tis approach has the tendency to fulfl high performance requirements and it provides the designers with several options to optimize their design according to their requirement [10]. Multiple processors system on chips (MPSoCs) con- nected through NoC have the ability to perform communi- cation and computation separately. MPSoCs featuring NoC can be used to perform various complicated tasks in parallel such as multimedia streaming, telecommunication protocols, and GPS [11]. A lot of efort has been put into the improvement of NoC’s components. Hindawi Publishing Corporation International Journal of Reconfigurable Computing Volume 2014, Article ID 806237, 8 pages http://dx.doi.org/10.1155/2014/806237