ORIGINAL PAPER Analysis and Simulation of Schottky Tunneling Using Schottky Barrier FET with 2-D Analytical Modeling Prashanth Kumar 1 & Adla Vinod 2 & Krishna Dharavath 3 & Brinda Bhowmick 4 Received: 18 November 2020 /Accepted: 2 December 2020 # Springer Nature B.V. 2021 Abstract A novel analytical model of surface potential for a double metal gate schottky barrier tunnelling (SBT) FET using schottky tunnelling with HfO 2 as gate dielectric is proposed. The presence of a schottky tunnelling at source-channel interface improves the drain current because of the advanced tunneling from one band-to- another band charge carriers in the area of the interface junctions. Moreover, the existence of the duel work-function- improved the conductivity and thus enhances the tunnelling probability, which increases device performance. The surface potential along the channel the model is examined using the two-dimensional (2-D) Poisson equation with suitable boundary conditions and shows a major part in the design of the shortest distance between source/channel and the drain-source current. Due to its high tunnelling increases on-state current, expressively reduced off-sate current, the proposed device represents one of the reliable model to substitute complementary metal-oxide- semiconductor (CMOS) technology. The results of the analytical model are confirmed against those attained using the silvaco device simulator. Keywords Schottky tunneling . Hetero-structure . Dielectric . Electric field . Analytical model . Lower bandgap material 1 Introduction Reducing the measurements of CMOS (complementary metal-oxide transistors) getting sub-100 nm ranges, conven- tional MOSFETs shows numerous difficulties like OFF-state leakage currents, high sub-threshold slope, and several other short channel effects (SCE). These difficulties clue to an ad- vanced power ingesting in scaling the supply voltage. Therefore, to incredulous these problems an unconventional to MOSFETs, SB FETs have been extensively premeditated [1–4]. In SB FET devices show essential benefits such as protection to short channel effects, gate lengths scaled up to sub-10 nm dimensions and low Source/Drain series resistance [5, 6]. Though, they endure from two main limitations as associated with their traditional equivalents, i.e. a low on- state current (I ON ) and high off-sate current [7–9]. Therefore, to improve the on-state current of the SB-FET, many catego- ries of research have been reported [10], though, for the de- creasing of off-state current, the significant struggle is quite essential. Now, a few research reports [11–13], this severe off- sate was decreased by introducing a Si 3 N 4 thin film among the Source-channel interfaces and Drain– channel interfaces. Furthermore, by extension between drain-channel interface a field-induced and retaining a recessed design with asymmetric Source/Drain contacts. But, nobody stated that above- methods are optimal for SB FET design. These techniques mainly rise fabrication difficulty and are complex to accept for nanoscale device executions. This encouraged us to im- prove a novel double metal gate schottky barrier tunnelling (SBT) FETs to facilitate a higher on-state current and switching ratio Ion/Ioff. Hence, a new analytical surface- potential based model for a double metal gate schottky barrier tunneling (SBT) FET is presented. The source as metal is developed in the source region of the tunneling model, which * Prashanth Kumar prash.034@gmail.com 1 School of Electronics Engineering, Vellore Institute of Technology (VIT), Chennai, India 2 Department of Electrical and Electronics Engineering, Marri Laxman Reddy Institute of Technology and Management Dundigal, Hyderabad, Telangana 500 043, India 3 Department of Electronics and Communication Engineering, Vardhaman College of Engineering, Hyderabad, Telangana 501218, India 4 Department of Electronics and Communication Engineering, National Institute of Technology, Silchar, Assam 788010, India Silicon https://doi.org/10.1007/s12633-020-00879-3