Low-Power Hardware Synthesis from TRS-based Specifications Gaurav Singh and Sandeep K. Shukla FERMAT Lab, Electrical and Computer Engineering, Virginia Tech, Blacksburg, VA. Email: {gasingh,shukla}@vt.edu Abstract— Synthesis from guarded atomic actions used for high-level descriptions of hardware designs has been shown to be a successful methodology for generating efficient designs [1]. This methodology uses CAOS (Concurrent Action Oriented Specifications) for hardware description which is based on the idea of Term Rewriting Systems (TRS’s) [2], [3]. A prime example of CAOS is Bluespec where the behavior of a design is described using various guarded atomic actions. Hardware synthesis from such specifications can infer more parallelism than is possible from the traditional methods of behavioral synthesis using CDFGs (control data-flow graphs) [4], [5], [6]. Hardware implementations generated from CAOS can exploit the parallelism germane in the computation and execute maximal set of actions concurrently in order to reduce the latency of the design. The concurrent execution of the actions enhances the performance of the hardware designs in terms of the delay but high power consumption may become an issue when multiple such actions are executed concurrently. Thus, there is a need to reduce power consumption during the CAOS-based synthesis. In this paper, we consider a CAOS similar to Bluespec’s model of computation and present two strategies targeting the reduction of peak power and dynamic power in designs generated from such specifications. One strategy uses the re-scheduling of the atomic actions to generate a low-power schedule whereas the other exploits the factorization as well as the re-scheduling of the actions for power reduction. I. I NTRODUCTION In the Concurrent Action Oriented Specifications (CAOS), the behavior of a design is described in terms of guarded atomic actions at a level of abstraction higher than RTL. In designs generated from such specifications, multiple actions can execute concurrently in the same clock cycle. The con- current execution of actions may result in high peak power and dynamic power consumption in the hardware generated from such specifications. Peak power becomes an issue if large number of actions are executed in the same clock cycle. This is undesirable due to packaging, cooling and reliability considerations. Furthermore, maximal set of actions executing in each clock cycle implies that more hardware units are working in parallel and results in high switching activity in such designs. This leads to high dynamic power consumption which increases the heat dissipation of the system and limits its battery life. Therefore, in designs generated from CAOS, strategies targeting the reduction of these power consuming activities are required [7]. Power savings in such hardware implementations can be achieved by re-scheduling the execution of the actions of a design to arrive at a power-efficient schedule that meets the timing requirements of the design and is functionally equivalent to the original schedule based on the maximal con- currency. While re-scheduling the actions for power savings, dependency constraints among various actions of the design need to be satisfied to arrive at a power-efficient schedule. Different types of dependency relationships can exist among the actions of a design and these dependencies guide the appropriate low-power strategies that can be applied to a given design. Factorizing the actions of a design into smaller actions can also be used to achieve power reduction. The execution of the parts of an action will be constrained by the dependencies among the different parts of the same action as well as their dependencies with the other actions of the design. This paper is organized as follows. Section II reviews some related work done in the domain of low-power behavioral synthesis. Section III discusses CAOS, dependency relation- ships among the actions, and other details related to the scheduling of the actions of a design. Section IV discusses various strategies that generate power-efficient schedules of the actions of a design based on their dependency relationships. A proof sketch of the functional equivalence of the generated low-power schedule with the original schedule is provided in Section V. In Section VI, we present example applications of various strategies presented in this paper and discuss the effects of these strategies on the power consumption and performance of a design. And Section VII concludes this paper by discussing the ongoing and future work. II. RELATED WORK [8], [9] present two heuristics targeting the minimization of the peak power and the dynamic power in the designs generated from CAOS. The power reduction strategies discussed in this paper are different from the ones in [8], [9] as follows - 1) In [8], [9], heuristic for peak power minimization considers a single cycle of the original schedule at a time and throttles the parallelism to meet the peak power constraint of the design. On the other hand, the strategies in this paper consider the actions executing over the multiple clock cycles of the original schedule and re-schedules these actions such that the degradation 1-4244-0421-5/06/20.00 ©2006 IEEE 49 2006 4th IEEE/ACM International Conference on Formal Methods and Models for Co-Design 1-4244-0421-5/06/$20.00 ©2005 IEEE 49