BOTTOM-UP TESTING METHODOLOGY FOR VLSIl J.P. Teixeira, zyxwvutsrq C.F.B. Almeida, J.A. GrScio, P.A. Bicudo, A.L. Oliveira, N. Rua INESC, IST, Rua Alves Redol, no 9, 3', 1000 Lisboa, Portugal Abstract A new testing methodology for digital VLSI circuits is proposed, based on the definition of a realistic fault list, which depends on the technobgy, the manufacturing pro- cess and the IC layout. Automatic fault listing is carried out by a hierarchical zyxwvutsrqpo Layout-to-Fault Extractor, LIFE. Fault list compression is performed, according to user-defined fault listing objectives. Test pattern validation is made by means of an accurate SWItch-level Fault simulator with Timing information capabilities, SWIFT. The methodology and the correspondent software tools can be used in the IC design and production testing environments. At present, the two software tools are to be included in the ICD tool box zyxwvutsrqp [8], in a workstation-based IC design environment. I. Introduction The traditional testing strategy aims at developing high- quality test patterns to ensure high fault coverage. How- ever, this measure of testing eficiency may prove to be un- reliable zyxwvutsrqpo [ 11, since the fault list is made assuming a logic-level representation of the circuit, and the industry-standard sin- gle stuck-at model. In fact, specially for MOS technologies, a significant amount of physical failures can occur, whose effect on circuit functionality cannot be described by the stuck-at model. This is the case of stuck-open and bridging faults. Their presence in digital ICs can be very disturbing, since the computational costs of test pattern generation and validation, and the costs of test application significantly in- crease when those faults have to be taken into account. However, if some of those faults are really likely to occur, we cannot ignore them. The traditional strategy deals with this problem by deriving test patterns achieving nearly 100 % fault coverage for stuck-at faults, and hoping that the overall defects level will be low. The main reasons for this strategy are that (1) some of those non-conventional faults can be detected by test patterns generated for stuck-at de- tection, and (2) the definition of a manageable subset of all possible shorts and breaks (potential shorts and breaks 121) is difficult. However, the testing efficiency thus achieved can be very disappointing, specially for CMOS circuits [3], even with nearly 100 % fault coverage for stuck-at faults. Therefore, in order to achieve a reliable and cost effective 'This work was supported in part by the EEC, in the context of the Esprit 991 Project, 'Multiview Design Systeni ICD'. testing, it is mandatory to establish, for each IC, a realis- tic fault list. If information on the physical failure modes (PhFMs) likelihood of occurrence is available, fault and test pattern ranking can further decrease test costs. In order to achieve these goals, a bottom-up methodology is required. In this paper, a bottom-up testing methodology for MOS digital VLSIs is proposed. It relies on (1) the development and automatic extraction of a realistic fault list, for each IC, taking into account the technology, the fabrication pro- cess (when available) and the circuit layout, (2) a reliable test validation, by means of accurate switch-level fault sim- ulation, (3) the development of high-quality test patterns (in case of off-line testing) to detect the listed faults, and zy (4) test pattern ranking (when possible), in order that the most likely circuit faults (CFs) are scheduled to be tested first. The testing methodology is presented in section 11. A new software tool, a hierarchical layout-to-fault (L-to- zyx F) extractor is described in section 111. In section IV, a new, concurrent, switch-level fault simulator with timing information is presented. Finally, section V describes the preliminary results obtained with the software tools, and discusses the major spin-offs of our work. 11. Testing Methodology The need for the definition of a realistic fault list has been already stressed in the previous section. The emphasis here is on how we can make it in a way amenable to be used in a workstation-based IC design environment, to help the designer in generating and validating the appropriate test patterns. The most likely CFs an IC can experience depend on the technology, on the manufacturing process and on the actual layout. Recently, work has been carried out on the char- acterization of CF's likelihood of occurrence 141 based on a process-oriented analysis of spot defects mechanisms. We believe that some specific, process-dependent defect mech- anisms should also be taken into account, which are not simply mask-dependent defects. As an example, open lines due to metal breaks are not only dependent on the planar density of defects in metalization, but also on step-coverage problems: in fact, they are more likely to occur in Al/poly cross-overs. Other authors have presented information, for given processes, on the likelihood of occurrence of PhFMs in MOS technologies [5], [6]. Hence, for a given process, the manufacturer can establish a ranked list of the most CH2584-1/88/0000-0100 $1.00 zyxwvutsrqp 0 1988 IEEE 16.6.1 IEEE 1988 CUSTOM INTEGRATED CIRCUITS CONFERENCE