J Comput Electron (2012) 11:321–329 DOI 10.1007/s10825-012-0409-8 Contribution to the modeling of a non-ideal Sigma-Delta modulator Abdelghani Dendouga · Nour-eddine Bouguechal · Souhil Kouda · Samir Barra · Brahim Lakehal Published online: 22 June 2012 © Springer Science+Business Media LLC 2012 Abstract One major issue facing the design and the sim- ulation of complex circuits, such as Sigma-Delta modula- tors (M), is the relatively large computing-time; required when using transistor level based simulators. Hence, high- level system modeling is suitable to achieve a time-efficient IC design. In this scope, the aim of the present work is to de- velop an enhanced model for a switched-capacitor second order sigma delta modulator. Besides the numerous effects, already included in the standard models, many additional non-idealities aspects have been taken into consideration. Namely, the DC nonlinearity behavior of both: the opera- tional amplifier (OP-AMP) and the switches ON-resistance. The obtained model permits, thus, more accurate prediction of the relative signal-to-noise ratio (SNR), compared to the standard one. Keywords Oversampling modulators · ADC modeling · Switched capacitor · Charge injection · Clock feed through A. Dendouga ( ) · N.-e. Bouguechal · S. Kouda · S. Barra · B. Lakehal Advanced Electronics Laboratory, University of Batna, Avenue Chahid Boukhlouf Mohamed El Hadi, 05000, Batna, Algeria e-mail: dendouga_gh@hotmail.com A. Dendouga Microelectronic and Nanotechnology Division, Centre de Développement des Technologies Avancées (CDTA), 20 Août 1956, Baba Hassan, BP17, Algiers 16303, Algeria 1 Introduction Due to their noise shaping behavior and their low sensitivity to circuit imperfections, oversampling converters have be- come popular for high-resolution medium-to-low-speed ap- plications. Oversampling data converters are able to achieve over 20 Effective Number Of Bits (ENOB) resolution at reason- ably high conversion speeds by relying on a trade-off. They use sampling rates much higher than the Nyquist rate, typ- ically higher by a factor between 8 and 512, and generate each output utilizing all preceding input values [2, 3]. The most popular approach is based on a sampled-data solu- tion with a Switched Capacitor (SC) implementation. For this reason, we will focus on the case of SC modulators in this paper. Given the diversity of architectures implementing converters, there cannot exist a generic model for all ADCs. Each architecture implementation of a converter requires its own model. In this paper we analyze the performances of a second order sigma-delta modulator including non-idealities and compare it to its ideal model. Modeling of analog-to-digital converter (ADC) compo- nents, as well as of digital measuring systems based on ADCs, allows the device behavior to be predicted with only a few preventive experiments. For this reason, in the last years, a great deal of scientific interest has been directed to ADC modeling also for metrological aims. A model turns out to be useful for investigating the ADC metro- logical behavior in several operating conditions during the main phases of development: design, evaluation and im- provement. In ADC design, the pre-eminent intrinsic error source is the quantization, and theoretical fundamental stud- ies have been devoted to this topic by specialized research groups.