Abstract—FinFET, which is a double-gate field effect transistor (DGFET), is more versatile than traditional single-gate field effect transistors because it has two gates that can be controlled independently. Usually, the second gate of FinFET transistors is used to dynamically control the threshold voltage of the first gate in order to improve the performance and reduce leakage power. However, we can also utilize FinFET’s second gate to implement circuits with fewer transistors. This is important since area efficiency is one of the main concerns in circuit design. In this paper, a novel scheme of implementing a majority gate and a 2-1 MUX by using both gates of FinFET transistors as inputs is presented. Simulation results show that FinFET logic implementation has significant advantages over static CMOS logic and pass transistor logic in terms of power consumption and cell area. Index Terms— FinFET, low power circuit, logic synthesis, combinational logic, independent gate. I. INTRODUCTION As the size of transistors has scaled down, so have many digital applications. Cell phones, laptops, sensors, and many other applications all shrunk in size over the last few decades and they are more and more portable. For this to happen, chips in these digital applications have to be designed to optimize the number of transistors used, the fewer the better. In this case, pass transistor logic is an attractive solution because a circuit can usually be implemented in pass transistor logics with around half of the number of transistors required for static CMOS implementation. However, pass transistor logic allows inputs to be tied to the source and the drain of a transistor, thus create possible situations where NMOS has to drive a logic 1 and PMOS has to drive a logic 0. Since NMOS is not a good pull up device, the output of a pass transistor circuit will suffer from a voltage drop V th and never achieve a full voltage swing to V DD . With the continuing scaling of supply voltage, this voltage drop cannot be tolerated. The additional back gate of a FinFET gives circuit designers many options. The back gate can serve as a secondary gate that enhances the performances of the front (primary) gate. For example, if the front gate voltage is V DD (transistor is ON) the back gate can be biased to V DD to provide bigger current drive, which reduces transistor delay. If the front gate voltage is 0 (transistor is OFF), the back gate can be biased to 0, which raises the threshold voltage of the front gate and reduces the leakage current. Most recent FinFET circuit researches, such as FinFET SRAM [1], focus Manuscript received July 3, 2009. Michael C. Wang was a graduate student at Princeton University, Princeton, NJ 08544 USA. (e-mail: mcwang@alumni.princeton.edu). on utilizing the back gate to improve circuit performance. On the other hand, the back gate can also be used to reduce the number of transistors needed to implement many logic functions. For a NFinFET, the transistor turns on if either the front gate or the back gate is V DD – this is equivalent to two NMOS transistors in parallel. Recent researches, such as a 3-transistor FinFET NAND gate [2], utilize this property. However, we have not seen any research that utilizes this property beyond a simple logic gate such as a NAND gate. The focus of this paper is to expand the idea of using both gates of FinFET as inputs to more complicated logic circuits, and provide insight on how to design a FinFET-based circuit with independent inputs for any logic function. In Section II and Section III, we will propose a novel FinFET majority gate and a 2-1 MUX. In Section IV, we will present simulation results. We conclude the paper in Section V. II. FINFET MAJORITY GATE A majority gate is commonly used in a full adder. A typical majority gate has three inputs and one output. If more than half of the inputs are 1, it returns a 1 on the output, otherwise it returns a 0. Table 1 shows the truth table of a 3-input majority gate. Schematics of three different implementations of a majority gate are shown in Fig. 1 (from left to right: Low Power, Area Efficient FinFET Circuit Design Michael C. Wang, Princeton University Table 1. Truth table of a 3-input majority gate A B C Out 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1 Table 2. Truth table of a 2-1 MUX A B S Out 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 1 Proceedings of the World Congress on Engineering and Computer Science 2009 Vol I WCECS 2009, October 20-22, 2009, San Francisco, USA ISBN:978-988-17012-6-8 WCECS 2009