Low Voltage Floating Supply in Monolithic High Voltage Technology for High dV/dt Applications E. Dallago, S. Ruzza, G. Venchi Power Electronics Laboratory Department of Electrical Engineering University of Pavia Via Ferrata 1 – 27100 Pavia – Italy Email: [dallago,ruzza,pepo]@power0.unipv.it S. Morini International Rectifier IC Motion Group Via Trieste 25 – 27100 Pavia – Italy Email: smorini1@irf.com Abstract- This paper presents two alternative evolutions of the previous presented floating power supply in monolithic high voltage technology. These circuits are used for feeding front-end circuitry realized inside the floating pocket of a current sensor chip which transduces the phase current of a triphase AC servodrive motor. The main feature of this supply is that the floating n-epi pocket it is realized in, is biased with a voltage lower than the maximum voltage value present in the pocket itself. The presented schemes are not affected by the charge injection problem caused by high dV/dt typical of this applications. Results of the most relevant simulations are reported. The circuits have been included in two test chip whose microphotograph is shown. I. INTRODUCTION In AC servodrive applications driven by a triphase inverter the phase current is often sensed using a shunt resistor connected between the X node and the load (see Fig.1). In fact, in such applications, the control of the motor torque is fundamental to improve the performance of the servodrive. Being the torque proportional to the phase current, it is necessary to have this data available at each instant. On the contrary, using a shunt resistor on the DC- of the inverter or in series to the IGBT emitter terminal makes the current data available only for short periods of time alternated with blind intervals. A current sensor chip realized in monolithic high voltage technology transduces the voltage signal provided by the shunt on the motor phase. Since the shunt signal is available continuously, it is possible to realize an input filter for the front-end circuitry which removes current harmonic components useless for the control [1]. In such applications, front-end circuitry are included in a floating n-epi pocket referred to the X node, epitaxialy grown on a p-type substrate. This pocket is characterized by a particular geometric shape that allows the n-epi/p-sub junction to withstand a high reverse-bias voltage. Resurf ® technique [2-6] is generally employed to properly shape the electrical field. Therefore, the junction breakdown can be as much as 1200V. In this way, useful signal can be acquired by rejecting the common mode present on the X node (DC+ or DC- in Fig.1). Typically, a bootstrap capacitor (C B ), is used to supply the floating side of the chip. Capacitor C B is charged by a 15V source (V A ) when the low side IGBT is closed, while it provides V FX =15V when the high side IGBT is closed, to comply with power transistor drive requirements. Supply voltage V FX is affected by significant amount of ripple due to the charging and discharging cycles on C B . High voltage technologies can benefit from the continuous size reduction of the MOSFETs to develop signal processing parts. In fact, the used technology provides 2µm, 20V MOSFETs and high performance 0.5µm, 5V MOSFETs. If V FX is used to bias the floating n-epi pocket and to supply the front-end circuitry, this signal circuitry needs to be realized with 20V MOSFETs. Hence, to exploit the 5V MOSFETs, a structure called Low Voltage Floating Supply (LVFS) must be realized which is capable of deriving a stable low voltage supply from the V FX voltage. Different solutions of LVFS could be implemented [7]. Some of these increase the costs or have a negative impact on the performances of the realized system. Others need a modification of some process steps which require expensive and time consuming qualifications of the entire process. Two topologies which allow a fully integrated LVFS to be realized in the same n-epi pocket where front-end circuitry is implemented have been presented in [8] and are briefly described in section II. In inverter applications they are affected by charge injection phenomena during dV/dt and this issue is also described in section II. The improved topologies are presented in section III, while the results of the most important simulations are reported in section IV. II. THE PROPOSED LVFS STRUCTURE The proposed structure the LVFS topology to be realized in the same n-epi pocket where front-end circuitry is implemented. Therefore, the n-epi pocket is biased directly by the output voltage of the LVFS circuit and not by V FX , which is the maximum voltage value available in the pocket. Being the technology designed to be used with the floating n-epi pocket biased by the voltage supply V FX , which is also the highest voltage value it contains, it was necessary to ensure that all junctions were reverse-biased under all working conditions. This result was obtained connecting to V FX only the drain terminal of n-channel MOSFETs in 20V technology and polysilicon resistors, (insulated because of their physical structure). The n-channel provided the supply output V OUT =5V 1024 1-4244-0655-2/07/$20.00©2007 IEEE