Int. J. Embedded Systems, Vol. 6, No. 4, 2014 319 Copyright © 2014 Inderscience Enterprises Ltd. Hardware-software architecture for priority queue management in real-time and embedded systems N.G. Chetan Kumar and Sudhanshu Vyas Department of Electrical and Computer Engineering, Iowa State University, 2215 Coover Hall, Ames, IA 50011, USA E-mail: ckng@iastate.edu E-mail: spvyas@iastate.edu Ron K. Cytron and Christopher D. Gill Department of Computer Science and Engineering, Washington University in St. Louis, 1 Brookings Dr., St. Louis, MO 63130, USA E-mail: cytron@cse.wustl.edu E-mail: cdgill@cse.wustl.edu Joseph Zambreno and Phillip H. Jones* Department of Electrical and Computer Engineering, Iowa State University, 2215 Coover Hall, Ames, IA 50011, USA E-mail: zambreno@iastate.edu E-mail: phjones@iastate.edu *Corresponding author Abstract: The use of hardware-based data structures for accelerating real-time and embedded system applications is limited by the scarceness of hardware resources. Being limited by the silicon area available, hardware data structures cannot scale in size as easily as their software counterparts. We assert a hardware-software co-design approach is required to elegantly overcome these limitations. In this paper, we present a hybrid priority queue architecture that includes a hardware accelerated binary heap that can also be managed in software when the queue size exceeds hardware limits. A memory mapped interface provides software with access to priority-queue structured on-chip memory, which enables quick and low overhead transitions between hardware and software management. As an application of this hybrid architecture, we present a scalable task scheduler for real-time systems that reduces scheduler processing overhead and improves timing determinism of the scheduler. Keywords: priority queue; hardware-software co-design; real-time and embedded systems; hardware scheduler. Reference to this paper should be made as follows: Kumar, N.G.C., Vyas, S., Cytron, R.K., Gill, C.D., Zambreno, J. and Jones, P.H. (2014) ‘Hardware-software architecture for priority queue management in real-time and embedded systems’, Int. J. Embedded Systems, Vol. 6, No. 4, pp.319–334. Biographical notes: N.G. Chetan Kumar is a PhD student in the Department of Electrical and Computer Engineering, where he is working with Prof. Phillip Jones. He completed his BS in Electronics and Communication at Visveswaraya Technological University, Bangalore, India in 2007. His research interests include embedded and real-time systems and hardware/software co-design. His current research focuses on developing techniques to improve predictability in execution of core system operations in real-time systems, using hardware-software co-design approaches. Sudhanshu Vyas is a graduate student pursuing his PhD at Iowa State University. He joined ISU in the Fall of 2009. Before joining, he received his BE from Birla Institute of Technology in Electronics and Communication Engineering in 2006 and worked at CG-CoreEl, an embedded systems company based in Bangalore. His research interests include reconfigurable architectures, embedded systems, control systems and FPGA fault tolerance.