Relative Scheduling under Timing Constraints: Algorithms for High-Level Synthesis of Digital Circuits David C. Ku Giovanni De Micheli Center for Integrated Systems Stanford University Abstract Scheduling techniques are used in high-level synthesis of integrated circuits. Traditional scheduling techniques assume fixed execution delays for the operations. For the synthesis of ASIC designs that interface with external signals and events, timing constraints and operations with unbounded delays, i.e. delays unknown at compile time, must also be considered. We present a relative scheduling formulation that supports operations with fixed and unbounded delays. In this formulation, the start time of an operation is specified in terms of offsets from the set of unbounded delay operations called anchors. We analyze first a novel property called well-posedness of timing constraints that is used to identify consistency of constraints in the presence of unbounded delay operations. We present an algorithm that will transform an ill-posed constraint graph into a minimally serialized well-posed constraint graph, if one exists. The anchors are then checked for redundancy, and we identify the minimum set of anchors that are required in computing the start time. We present an algorithm that schedules the operations relative to the anchors, which yields a minimum schedule that satisfies the timing constraints, or detects if no schedule exists, in polynomial time. Finally, we describe the generation of control logic from the resulting relative schedule. Analysis of the optimality and complexity of the algorithm is presented. 1 Introduction High-level synthesis of digital hardware from behavioral specifications has been shown to be a practical and efficient means of design. Many tasks need to be performed in high-level synthesis to transform an abstract hardware representation into an interconnection of modules and a corresponding control unit. Scheduling and module binding are among the most important tasks in order to synthesize circuits that are efficient in terms of area and performance. These two problems can be modeled as scheduling under resource constraints, which unfortunately is an intractable problem [1]. For this reason, most high-level 1