Using Non-Trivial Logic Implications for Trace Buffer- based Silicon Debug Sandesh Prabhakar Michael Hsiao Electrical and Computer Engineering Electrical and Computer Engineering Virginia Tech, Blacksburg, VA, USA e-mail: sandeshp@vt.edu Virginia Tech, Blacksburg, VA, USA e-mail: hsiao@vt.edu Abstract – An effective silicon debug technique uses a trace buffer to monitor and capture a portion of the circuit response during its functional, post-silicon operation. Due to the limited space of the available trace buffer, selection of the critical trace signals plays an important role in both minimizing the number of signals traced and maximizing the observability/restorability of other untraced signals during post-silicon validation. This paper presents a new method for trace buffer signal selection for the purpose of post-silicon debug. The selection is performed by favoring those signals with the most number of implications that are not implied by other signals. Then, based on the values of the traced signals during silicon debug, we introduce an algorithm which uses a SAT-based multi-node implication engine to restore the values of untraced signals across multiple time-frames. Experimental results for sequential benchmark circuits showed that the proposed approach selects the trace signals effectively, giving a high restoration percentage compared with other techniques. Index Terms – Silicon debug, Logic implication, Trace-signal selection, State Restoration, Forward Learning. I. INTRODUCTION Silicon Debug is a technique used to detect and locate the undetected design bugs and/or manufacturing defects which may have escaped the pre-silicon verification or manufacturing test. There are two existing types of silicon debug: scan-based and trace buffer-based. Design-for-debug (DFD) hardware is needed in both these approaches. In the scan-based approach, the internal scan chains are reused wherein the captured data from the internal state elements corresponding to specific triggering events are off-loaded (or dumped) through the scan chains. In [6] and [7], the authors discuss post-processing algorithms which can be used to identify the failing state elements from the scan dump data. In [5] a method was proposed which utilizes backward and forward logic implications of the scan-dump values to restore more circuit gate values. However, the main disadvantage of the scan-based approaches is the repeated scan-dumps. Many scan dumps would be both costly and cumbersome for silicon debug. The trace buffer-based approach is a complementary technique which can be used to acquire continuous data. An embedded logic analyzer (ELA) [8] is used for sampling internal signal data into on-chip trace buffers. This is followed by a post processing stage [9] wherein the sampled data is off- loaded for analysis to reconstruct internal signal values and identify functional bugs. Two parameters limit the amount of data which can be acquired by the trace buffer: the buffer’s depth and width. The former limits the number of samples that can be stored and the latter limits the number of trace signals which can be sampled and recorded in each clock cycle [3]. In [4], [8] and [10]-[12], methods for ELA design improvement were proposed. In [13]-[15] trace compression methods were proposed to increase the number of trace signal samples. However, because of the trace buffer memory limitation, the selection of the critical trace signals which can maximize the restoration of the missing signal values is highly desirable. In [1], [2] and [3], algorithms were proposed for trace signal selection and state restoration using restorability metrics that consider both the topology and behavior of logic gates. In this paper, we present a new algorithm using a logic implication-based [16] learning approach to intelligently select the trace signals. We favor selecting those signals which contain more implications that are not implied by other signals. We show that our trace selection method is efficient and is able to achieve better restoration than other techniques. The rest of the paper is organized as follows. Section II gives a brief overview of static logic implications [16] and defines parameters used to evaluate the quality of trace selection. Section III discusses the proposed approach for trace buffer signal selection. Section IV introduces the algorithm used for state restoration. Section V reports experimental results, and Section VI concludes the paper. II. PRELIMINARIES A. Static Logic Implications Let us consider a circuit with n gates. Logic implications determine the effect of assigning logic values (0 or 1) to one or more gates in the circuit. The implications are stored using a directed implication graph G (V, E) where V (vertices)  the set of 2n nodes corresponding to both value assignments (0 and 1) and E (edges)  single-node implications. For sequential circuits, each edge is annotated with an integer weight w that indicates the number of time frames that this implication spans. Static logic implications can be sub-divided into direct, indirect and extended backward implications [16]. Indirect and extended backward implications use logic simulation as well as the contra-positive and transitive laws extensively. These learned implications are thus non-trivial. These non-trivial logic implications are used to form a new restorability metric to drive the trace signal selection. The 2009 Asian Test Symposium 1081-7735/09 $26.00 © 2009 IEEE DOI 10.1109/ATS.2009.20 135 2009 Asian Test Symposium 1081-7735/09 $26.00 © 2009 IEEE DOI 10.1109/ATS.2009.20 135 2009 Asian Test Symposium 1081-7735/09 $26.00 © 2009 IEEE DOI 10.1109/ATS.2009.20 131