A Simple Realization of Negative Type Differential Difference Current Conveyor (DDCC) MUHAMMED A. IBRAHIM Department of Electrical Engineering, College of Engineering University of Salahaddin Kerkuk Street, Erbil IRAQ mabdulbaki@hotmail.com Abstract: - A simple topology for the realization of negative type differential difference current conveyor (DDCC-) is presented. The proposed topology is based on floating output transconductor (FOT) circuits. A CMOS realization of this type current conveyor, which is made up from floating current sources (FCS), is given. Design details and simulation results using PSPICE are given to verify predictions. Key-Words: - DDCC, Current Conveyor, FOT, CMOS, FCS. 1 Introduction Many new types of current conveyors have been presented since the first introduction in 1968 (CCI) [1]. They have been the second-, the third- generation current conveyors (CCII, CCIII) [2,3] and the inverting second-generation current conveyor (ICCII) [4]. These building blocks have found applications in many fields. The most successful type is CCII. Although the CCII can be used to implement many high performance analog circuits, it has an apparent disadvantage of having only one high input voltage (the Y terminal). This disadvantage becomes evident when the CCII is required to handle differential signals, as in the case of an instrumentation amplifier. Moreover, in continuous-time analog signal processing, conventional CCII cannot be used in applications demanding differential or floating inputs like impedance converter circuits. Then the design of such an amplifier requires two or more CCIIs. This problem has been solved with the help of special current conveyors, named differential difference current conveyor (DDCC) and differential voltage current conveyor (DVCC) [5,6]. In this paper, a simple topology based on floating output transconductor (FOT) blocks and a CMOS realization of the negative differential difference current conveyor (DDCC-) based on floating current sources (FCSs) [7] are presented. Unlike the previous CMOS structures of the DDCC and DVCC [5,6], in the proposed circuit the negative output current is produced directly, i.e., without using inverting current mirror stages. 2 Proposed Circuit The proposed circuit implementation of the DDCC- is based on the block diagram shown in Fig. 1. Blocks g m1 and g m2 form the input stage, while the output stage is formed by block g m3 . All of the three blocks are FOT stages. Since the input current of the third FOT is zero the output currents of the first and the second FOT must be equal, i.e., 2 1 o o I I − = → 2 ) ( 1 ) ( 1 2 3 gm V V gm V V X Y Y Y − − = − (1) The gain between Y and X terminals depends on the transconductances g m1 and g m2 which must be equal in order to have the voltage property of DDCC which is 3 2 1 Y Y Y X V V V V + − = (2) A negative feedback is used in order to minimize the input impedance at the X terminal. It is worth noting that the negative type of the current conveyor isn’t adapted from the positive type one as in [5,6]. In contrast, the DDCC+ can be adapted from the DDCC- by adding another FOT as shown in the block diagram of Fig. 2. Many DDCC- realizations with different performance can be obtained according to the basic FOT circuit used. Fig. 3 shows the proposed DDCC- CMOS realization based on two balanced output currents structure named floating current source (FCS) [7] which requires no transistor matching constraint unlike the current mirrors structure. Essentially, this structure is just two matched CMOS inverters biased by two current sources and operates as an analogue transconductor stage. The transistors of the output stage provide two balanced output currents; one of Proceedings of the 11th WSEAS International Conference on CIRCUITS, Agios Nikolaos, Crete Island, Greece, July 23-25, 2007 37