One-Transistor Nonvolatile SRAM (ONSRAM) on Silicon Nanowire SONOS Seong-Wan Ryu, Jin-Woo Han, Dong-Il Moon, and Yang-Kyu Choi EECS, KAIST, Daejeon 305-701, Republic of Korea Email:ykchoi@ee.kaist.ac.kr , Phone: +82-42-350-5477, Fax: +82-42-350-8565 Abstract A o ne-transistor n onvolatile S RAM (ONSRAM) on a silicon nanowire (SiNW) SONOS is demonstrated. A nonvolatile memory (NVM) property is attained by employment of O/N/O gate dielectric stacks as an electron storage node, and SRAM functionality is achieved by exploiting latch phenomena of a floating body in SiNW. Abrupt inverter switching, superior sensing current (≥21µA), and robust interference immunity between SRAM and NVM verify the feasibility for the suggested ONSRAM. Introduction A partially-depleted (PD) FinFET was reported to enhance 1T-DRAM performance [1,2]; however it imposes a constraint on further scaling due to the tradeoff relation between the sensing margin and immunity to short-channel- effects (SCEs), as shown in Fig. 1. Recently, a bipolar- junction-transistor (BJT)-based 1T-DRAM demonstrated that a fully-depleted (FD) device can perform bi-stable memory operation with a wide sensing window and long data retention without a floating body region in PDSOI [3,4]. The latch-up caused by positive feedback on the parasitic BJT, which is normally an undesired phenomenon, displays a hysteresis loop with a steep subthreshold slope (SS), similar to impact–ionization metal-oxide-semiconductor transistors (I-MOS) [5] and tunneling field-effect transistors (TFET) [6] . These features can be explored for use in single transistor based SRAM operation [7]. In the present work, we demonstrate SRAM function in a single silicon nanowire (SiNW) MOSFET that has high SCEs immunity and propose a o ne-transistor n onvolatile SRAM (ONSRAM) for device- level fusion through the use of O/N/O layers as a floating gate and gate dielectrics, as illustrated in Fig. 2. A single ONSRAM chip to embody the one-transistor (1T) SRAM can replace a multi-chip-package (MCP) to stack SRAM as buffer memory and flash memory for low power, compact mobile electronic devices. Device Fabrication The process flow and photographs of the SiNW SONOS are illustrated in Fig. 3. The top silicon layer, having a thickness of 110 nm, in a silicon-on-insulator (SOI) wafer was thinned to 50 nm via oxidation and a wet-etch process. After delineation of the photoresist with 150-nm-line width, the photoresist was partially trimmed to 50 nm through an O 2 plasma ashing process. A 50-nm-width and -height top silicon was patterned and reduced to 30 nm by the thinning process. O/N/O of 3nm/7nm/12nm and n+ in-situ poly-Si layers were stacked sequentially and patterned simultaneously. Finally, S/D was formed by an implantation and activation process. 150 nm-long- and 50 nm-thick- devices were nominally used for the measurement. Results and Discussion A. NVM characteristics Despite a thick gate dielectric, the SiNW SONOS shows comparable program efficiency by a channel-hot-electron- injection (CHEI) mechanism and a steeper subthreshold slope (SS) due to high gate controllability as compared to a PD FinFET SONOS, as shown in Fig. 4. Full program and erase (P/E) were achieved at V G,PGM =11V and V G,ERS =-12V with a duration of 80 µsec at V D,PGM =4V and V D,ERS =4.5V, respectively. Acceptable charge retainability (∆V th =3.3V @ 10 year) was attained for the SiNW SONOS with an endurance characteristic of over 10 5 P/E cycles, as shown in Fig. 5. B. SRAM characteristics The bistable hysteresis and steep SS less than 20mV/dec were attributed to iterative impact ionization, which results in activation of a parasitic npn BJT. Current is thereby multiplied by a positive feedback loop, as illustrated in Fig. 6 [8]. To set up SRAM operation conditions, the latch-up voltage is examined for various V DS and V GS , as shown in Fig. 7. The parameter instability with respect to V D is shown in Fig. 8. Depending on V DS , less V th degradation and steeper SS were achieved for the thinner d NW despite 97-4244-5640-6/09/$26.00 ©2009 IEEE IEDM09-633 27.5.1