International Journal of Engineering Research and General Science Volume 3, Issue 2, March-April, 2015 ISSN 2091-2730 1119 www.ijergs.org Low Power-Delay-Product CMOS Full Adder Ankita Bhati, Prof. Vinod Kr. Pathak, Dr. Rita Jain Department of Electronics and Communication, LNCT, Bhopal, India, aankita.bhati @gmail.com Abstract— This paper shows an effective and improved circuit design for 1-bit full adder circuit with lesser energy required. The circuit is designed using total number of 9 transistors. The proposed circuit performance better in terms of power, delay, power delay product which is very easily shown by the simulation results. There is comparison of performance among proposed circuit with other pre-exist circuits in various literatures and this comparison shows higher reduction in Power-Delay-Product (pJ) of our proposed design. It has remarkably improved power consumption and temperature sustainability when compared with existing design. BSIM standard models are used for simulations. The proposed design gives faster response for the carry output and can be used to reduce more at higher temperature. Keywords— nMOS; pMOS; Adder; PDP, Delay. INTRODUCTION Addition is one of the fundamental arithmetic operations. It is used extensively in many VLSI systems such as microprocessors and applications specify DSP architecture. In addition to its main task which is adding two numbers, it is the nucleus of many other useful operations such as, subtraction, multiplication etc. In most of these systems the adder lies in the critical path that determines the overall performance of the system. The XOR gate is the basic building block of the full adder circuit. The performance of the full adder can be improved by enhancing the performance of the XOR gate. The main intention of reducing this transistor count is to reduce the size of XOR gate so that large number of devices can be configured on a single silicon chip thereby reducing the area and delay.[1]. Most of the time increasing the threshold voltage could limit performance loss but results get increased leakages [2]. There are some other techniques as well which are used for design of low power which includes clock gating along with dynamic voltage or frequency scaling [3] and [4]. Energy-efficiency is one of the most required features for modern electronic systems designed for portable applications.1bit Full Adder (FA) cell is the building block for most implementations of subtraction, addition operations. Full adder circuit is functional building block and most critical component of complex arithmetic circuits like microprocessors, digital signal processors or any ALUs. Almost every complex computational circuit requires full adder circuitry. The entire computational block power consumption can be reduced by implementing low power techniques on full adder circuitry To meet the rising demand, we advise a new energy efficient power adder by reducing the number of the MOS Transistor which reduces loss problem, considerably diminishing the power consumption compared to its peer design. So a new improved 9T l-bit full adder cell is presented in this paper. We have conducted simulation runs in different input patterns, varying voltages and temperatures. The reason to do these many simulations is to give a better confidence to how this new adder would perform under all possible practical applications. Results demonstrate improvement in threshold loss, power consumption and temperature sustainability. THEORETICAL BACKGROUND Full Adder circuit adds a pair of matching bits of the two different numbers which are expressed in binary form and carry from the earlier stage producing a sum with a new carry. Hence, it is also called a two input adder. Basically adder topologies are based on two XOR circuits (Module I and Module II) generating the sum and Module 3 made up of different topologies to generate the carry out as shown in fig.1. The Carry signal can obtained by using one MUX and one XOR output. Fig.1: Structure of Full Adder