© 2018 JETIR October 2018, Volume 5, Issue 10 www.jetir.org (ISSN-2349-5162) JETIR1810790 Journal of Emerging Technologies and Innovative Research (JETIR) www.jetir.org 71 Optimized Test Application Time and Test Data Volume Using LFSR for Combinational Circuits Muddapu Harika 1 , E. Lakshmi Prasad 2 1 M.tech in VLSI, JNTUA College Of Engineering, Ananthapuramu 2 Lecturer, Department of ECE, JNTUA College Of Engineering,Ananthapuramu Abstract- The main objective of this project is to reduce the application test data time and test data volume using customized LFSR for combinational ATPG and sequential ATPG circuits. There are many existing standard LFSRs are used for generating the test patterns but the proposed method able to reduce the application test data time and test data volume by selecting the appropriate seed value by using different characteristic polynomials. The main purpose of customized LFSR is to generate a limited number of bits to achieve test data compression. An LFSR will produce a pseudo-random sequence with a maximum length of (2 n-1 ) states (where n is the number of stages). The number of states can be reduced by selecting the appropriate characteristic polynomial for LFSR. The test application data and data volume can be reduced by selecting the appropriate seed value. Here, in this paper customized LFSR is designed with respect to 4-bit, 8-bit and 16-bit for all combinational circuits. Index Term:LFSR, Test compression, characteristic polynomial, data volume. 1. INTRODUCTION: The non-zero first state of the LFSR flip-flops is called the seed value.The LSFR technique is to produce the total of random test patterns based on the selection of the seed value. This approach is executed in three steps: in the first step, selecting the test vectors. In the second step, an exhaustive set of pseudo-random patterns is generated with a non-zero value as the initial seed. In the third step, a heuristic approach is made by comparing witha minimumnumber of ATPG patterns and the large set of random patterns. An N-bit LFSR produces the (Pseudo) random patterns initially from the seed value and continues to generate all possible 2 N-1 combinations. The number of faultsis distinguished by applying the random. By using an LFSR few patterns are enough to get good fault coverage. Later, to avoid the huge number of redundant patterns between the usage patterns, the LFSR can be loaded with an initial value to produce the group of patterns which are more useful to detect faults[1]. A test vector is considered as the seed (initial test vector) of that group based on the following factors. 1. Seed vector can produce all the successive patterns in the group of consecutive clock pulses. 2. The seed vector could be achieved with less number of clock cycles based on the above conditions. Test generation process strives to generate a test set which can detect all the targeted faults. Faults are usually of the same fault model, but a mix of faults fromvarious fault models can also be used[2]. The patterns in the test set are eventually proposed to detect defects occurring in the circuit. Test generation consists of two main steps: fault activation and fault propagation. Fault activation: Fault activation sets the signal on a given line to a given value, depending on the fault model[3]. For stuck-at faults, an opposite value is applied and determine the fault. Fault propagation: Fault effect propagation means to set proper values to the particular path inputs along with a selected path so that the path is sensitized and the fault effect can be observed at an observation point[4]. By test compaction or generation of compact tests, we mean the generation of minimal-sized test sets to achieve the desired fault coverage. Two methods exist to generate minimal test sizes. The first approach is to use extra hardware such as test points. Another method uses software techniques to produce minimal test set sizes[5]. In this work, we use software techniques. Several works have considered methods to generate small test sets. 2. RELATED WORK: Hellebrand et al. A new pattern are generated based on LFSR which is capable of providinga numeral primitive polynomial. These polynomials are generated by using the feedback taps of the LFSR. The generator producing sequences will eliminate linear dependence practically. By using this property to widen the encoding efficiency for test cubes to test faults will be difficult. So by reducing the linear dependences, many other applications are used.