An Efficient Implementation of 4x4 King Mesh Topology using Routing Technique T. Madhubala PG Scholar P. Karthika PG Scholar S. Sobana Assistant Professor Dept. of Electronics & Communication Engineering Dept. of Electronics & Communication Engineering Dept. of Electronics and Communication Engineering PSNA College of Engineering & Technology PSNA College of Engineering & Technology PSNA College of Engineering & Technology Dindigul, Tamil Nadu, India Dindigul, Tamil Nadu, India Dindigul, Tamil Nadu, India Abstract-In Network on Chip (NoC), the quantity of cores get increases step by step within the past few decades. This have an effect on the performance of the mesh and this ends up in evolution of new topological concept. The king topology provides the high grade evolution of the humanistic mesh and torus topologies. This network exhibits a variety of attention- grabbing characteristics that helps to achieve, reduced execution time of parallel processing applications. However, the long distance traffic might suffer from high transmission latency in mesh. The main aim of the proposed work is to reduce the quantity of hop counts by using XY routing and Weight based Path Selection (WPS) routing technique. That the speed of the system get improved and therefore the utilization of space and power consumption get reduced. Keywords- Topology, Routing Algorithm, Communication Network and Switching, Digital Subsystem. I. INTRODUCTION In System on Chip (SoC) the number of blocks in the IP modules getting rised in which the bus based architecture this reduce the performance of the system. Thus in cooperative communication bus design does not attain the desired bandwidth and other parameter measures. To enhance this, the usage of embedded shift network is meant and results in the evolution of Network on Chip (NoC). The most benefits of NoC architecture is scalability and suppleness. In NoC, topology of the network is extremely necessary to inter-connect the modules within the chip. There are various types of topological architectures are used to provide communication between subsystems. In network, the information are processed in the form of flits and packets. Where every single packet consist of header part and payload part. The payload portion of the packet consist of the original data and the header portion consist of sender address, destination address and control logic function. Network flow control is used to find the path how the individual packets are processed inside the network. The major principle of NoC architecture is the interconnection between the blocks. But the packet transmission is based on the routing technique. This techniques are used to identify the path of the data to process. This helps to work out the performance of the system. The main aim of the routing algorithms are to decrease the usage of in between switches and to reduce the latency. This additionally helps to balance the processing load of the channel. Performance of the network depends on the sort of topology and algorithms used to process. A. Topology Topological architecture play a major role in Network on Chip (NoC). This proceed with the physical layout and interconnection of the nodes and links in the network. The topology has a specialized impact on the processing performance and cost of the architectural design. Based on this routers are used as a switches are nodes to transfer the information. Those nodes are connected either by half duplex or full duplex link to communicate with their neighboring nodes. Fig. 1. A 4x4 mesh topological network The switches in between the sender node and receiver node is consider as the hops. Based on the number of hop counts, latency of the system get rise or fall. The number of switch hops is typically captured by the average hop counts. Various type of topological architectures have different path diversity. This provides the best opportunities for balancing the traffic loads across the multiple paths. NoC consist of various type of topologies such as Mesh, Torus, Star, Spin and Octagon. Most commonly used topological architecture in the integrated circuit design is mesh topology. International Journal of Engineering Research & Technology (IJERT) ISSN: 2278-0181 Published by, www.ijert.org RTICCT - 2017 Conference Proceedings Volume 5, Issue 17 Special Issue - 2017