TED+: A Data Structure for Microprocessor Verification Pejman Lotfi-Kamran, Mohammad Hosseinabady, Hamid Shojaei, Mehran Massoumi*, and Zainalabedin Navabi Electrical and Computer Engineering Department, Faculty of Engineering, University of Tehran, Tehran, Iran *California State University, CA, USA {plotfi, mohammad, shojai}@cad.ece.ut.ac.ir, massoumi@sbcglobal.net, and navabi@ece.neu.edu Abstract－Formal verification of microprocessors requires a mechanism for efficient representation and manipulation of both arithmetic and random Boolean functions. Recently, a new canonical and graph-based representation called TED has been introduced for verification of digital systems. Although TED can be used effectively to represent arithmetic expressions at the word- level, it is not memory efficient in representing bit-level logic expressions. In this paper, we present modifications to TED to improve its ability for bit-level logic representation while maintaining its robustness in arithmetic word-level representation. It will be shown that for random Boolean expressions, the modified TED performs the same as BDD representation. I. INTRODUCTION Boolean functions are often represented and manipulated by Decision Diagrams (DDs). Ordered Binary Decision Diagrams (OBDDs) [1] are the most commonly used form of decision diagrams in EDA applications [2]. Despite its widespread use, some classes of Boolean functions cannot be represented efficiently by OBDDs [3] [4]. For representing these classes of Boolean functions other decision diagrams are proposed and used. As an example, Ordered Functional Decision Diagrams (OFDDs) [5] [6] are proposed for better representing XOR based logic [7]. OBDDs and their variations have been successfully used in manipulating gate-level designs, but have limitations in representing arithmetic circuits. For representing arithmetic circuits, Word Level Decision Diagrams (WLDDs) are proposed. They use decomposition methods similar to the decomposition of Boolean functions, but at the arithmetic-level. MTBDDs [8] [9], EVBDDs [10], BMDs [11], HDDs [12], *BMDs [11], K*BMDs [13] are examples of WLDDs. They are graph-based representations of functions with Boolean domain and integer range; therefore an arithmetic function should be broken down into bit-level in order for it to be represented by WLDDs. With increasing complexity of digital systems, the need for higher level abstractions becomes more evident. TED [14] [15] [16] is proposed to satisfy this need. In TED, the decomposition of a function (Boolean or arithmetic) is performed along each word-level variable of the function using Taylor series expansions. It has been proven that with a special restriction on the ordering of function variables, TED becomes a canonical representation. TED can also be used for representing functions with Boolean domain and Boolean/integer range. Although TED has many advantages over WLDDs, its weak Boolean function manipulation is its main problem. When a design consists of word-level and bit-level parts (including Boolean parts), its TED occupies a large amount of memory. Today, many microprocessors have a large data-path and one or several controllers. Usually the data-path contains arithmetic circuits with vector size of 32-bit or longer and the controller has many bit-level signals for controlling the data- path operations. In such cases, WLDDs are not the best solution because they break arithmetic operations into their bit- level parts. This detailed representation is an overkill for RT- level verification of microprocessors, and significantly degrades the verification performance. On the other hand, TED, that has a good arithmetic representation for data path parts of a design, does not offer a good solution for Boolean manipulation for the controller parts. A solution is to use different Decision Diagrams for representing different part of a design. This solution leads to more difficulties in the verification process. Also using two or more different decision diagrams makes it hard and almost impossible to check equivalency of two designs, because equivalency of two designs does not mean that each of their parts are necessarily equivalent. The aim of this paper is to provide a unique representation for handling high-level verification of data-path and controllers. The key idea is that arithmetic operations encountered in the RTL specification are simple, e.g., x+y, x*y, etc. Therefore, it is proper to degrade the performance of algebraic representation of expressions that are not common in practical designs, and instead improve the performance of Boolean function manipulations. This paper provides a unique representation for efficiently representing typical algebraic equations encountered in data-path of today’s high performance processors. At the same time, our representation has a good Boolean function manipulation. This paper is organized as follows: Section 2 presents a brief overview of TED. In Section 3, our TED+ is introduced. In Section 4, Additive weights (as in k*BMD) will be added to the TED+ for better representation of arithmetic and Boolean functions. Experimental results are discussed in Section 5 and conclusions are presented in the last section. II. TAYLOR EXPANSION DIAGRAM TED is a graph-based representation that uses the Taylor series as its decomposition method [14] [15] [16]. The Taylor series expansion of a real differentiable function f(x) around x=0 is: 567 6C-2 0-7803-8736-8/05/$20.00 ©2005 IEEE. ASP-DAC 2005