Memory-less Pipeline Dynamic Circuit Design Technique Themistoklis Haniotakis Zaher Owda and Yiorgos Tsiatouhas University of Patras Department of Computer Engineering and Informatics 26500 Rio, Patras. Greece University of Ioannina Department of Computer Science 45110 Ioannina, Greece Abstract-A desirable characteristic of VLSI circuits is high speed operation. The use of dynamic circuit design techniques can provide high speed operation at lower silicon area requirements, compared to full static CMOS designs. Another common design technique in order to achieve high operating speed is the use of pipeline schemes. However, the higher the required operating frequency, the higher the number of stages we must implement in the pipeline. In addition, a limiting factor in cases with a large number of stages, are the restrictions imposed from the required memory elements. These memory elements not only increase the silicon area of the implementation but also restrict the maximum achievable frequency due to their internal delays. In this paper, we propose a memory-less pipeline design style, where the combinational part is implemented with dynamic circuits that offer the desirable high speed operation while the memory elements are eliminated due to an intelligent clocking scheme. Thus, the proposed design technique provides the advantage of high performance operation and at the same time compares favorably to preexisting approaches with respect to silicon overhead and power requirements. Keywords-Dynamic logic; Pipeline design, High performance. I. INTRODUCTION Dynamic CMOS logic is a well known high performance and low cost design style [1]. It provides circuits with low silicon area requirements compared to full static CMOS logic, while they operate 1.5 – 2 times faster than the corresponding full static CMOS logic circuits [2]. Due to these features dynamic circuits are widely used to speed up critical units in high performance CMOS microprocessors [3-7]. Among various schemes, Domino logic is the most frequently used dynamic design approach [1], [8]. Several Domino designs, effective for high performance operation, have been presented in [9]. An AND Domino gate design precharged by clock and data, which presents increased performance and reduced area requirements has been proposed in [10]. A modified Domino gate, called contention-free, has been proposed in [11] to resolve the trade-off between speed and noise margins. Low-power Domino logic designs, based on low-voltage swing techniques, have been presented in [12] and [13]. In addition, a clock delayed Domino logic design, with variable threshold keepers to reduce power consumption, has been proposed in [14]. Recently, a multi-valued Domino logic design technique, for high performance operation, has been presented in [15]. In this paper we present a new dynamic circuit design technique that allows the implementation of pipeline structures without the need of memory elements; instead it exploits a three phase clocking design style. The pipeline operation along with the memory elements elimination provides very high speed circuit realizations. The paper is organized as follows. In Section II the dynamic and Domino CMOS logic design styles are presented. Next, in Section III the proposed design technique is analyzed and in Section IV its advantages and disadvantages are discussed. Finally, in Section V experimental results are provided, while in Section VI the conclusions are drawn. II. DYNAMIC AND DOMINO CMOS LOGIC In the case of full CMOS logic two networks are implemented, a p-network connecting the gate output to the power supply V DD and an n-network connecting the output to ground (Gnd). If for a certain input combination the output value is logic “1” then an active (conducting) path through the p-network charges the output to V DD ; at the same time no active path exists through the n-network. In case that logic “0” is the output response, the n-network has an active path discharging the output while no active path exists in the p- network. An important attribute of the full CMOS logic is the inverting capability. An alternative approach in gate design is to use only the n- network and preset periodically the output to logic “1”. In case that a logic “0” value is required at the output an active path in the n-network discharges the output while in case that a logic “1” value is required no path is formed in the n- network to discharge the output which simply remains charged to V DD . This kind of operation requires two different phases the precharge and the evaluation phase. During the first phase (precharge) the output is set at logic “1”; while during the second phase (evaluation) the desired value is obtained. In that case there is no need for a p-network to charge the output. Instead a single pMOS control transistor (precharge transistor) is exploited to charge the output during the precharge phase. An additional nMOS control transistor (evaluation transistor) isolates the n-network from the ground and ensures that no discharge path is formed through the n- network during the precharge phase. During the evaluation phase the pMOS precharge transistor is inactive. Thus, during this phase, no “0” to “1” transitions can take place at the output. This implies that during the evaluation phase if an input combination discharges the output, the latter will remain 2010 IEEE Annual Symposium on VLSI 978-0-7695-4076-4/10 $26.00 © 2010 IEEE DOI 10.1109/ISVLSI.2010.42 201