A Schedulability Test for Software Migration on Multicore System Jung-Eun Kim ∗ , Richard Bradford † , Tarek Abdelzaher ∗ , Lui Sha ∗ ∗ Dept. of Computer Science, University of Illinois at Urbana-Champaign, Urbana, IL 61801, USA † Rockwell Collins, Cedar Rapids, IA 52498, USA Abstract—This paper presents a new schedulability test for safety-critical software undergoing a transition from single-core to multicore systems - a challenge faced by multiple industries today. Our migration model consists of a schedulability test and execution model. Its properties enable us to obtain a utilization bound that places an allowable limit on total task execution times. Evaluation results demonstrate the advantages of our scheduling model over competing resource partitioning approaches, such as Periodic Server and TDMA. I. I NTRODUCTION This paper presents a schedulability test to support migration of safety-critical software from single-core to multicore systems. The work is motivated by the advent of multicore processors over the last decade, with increasing potential for efficiency in per- formance, power and size. This trend has made new single-core processors relatively scarce and as a result, has created a pressing need to transition to multicore processors. Existing previously- certified software, especially for safety-critical applications such as avionics systems, underwent rigorous certification processes based on an underlying assumption of running on a single-core processor. Providers of these certified applications wish to avoid changes that would lead to costly recertification requirements when transitioning to multicore processors. Our paper provides a significant step toward supporting mul- ticore solutions for safety-critical applications. It does this by building on three separate analysis methods that previously had not been applied together to multicore systems. These are: (i) Utilization bound analysis using task period information (ii) Conflict-free I/O scheduling, and (iii) Global priority assignment across all tasks on a core, irrespective of application (defined by a group of tasks), while enforcing application budgets. Our schedulability analysis can be viewed as an extension to the classical Liu and Layland (L&L) schedulability bound [1]. When known values of task periods are used in the analysis, the bound becomes even better (i.e., less restrictive), often significantly so. This is because the L&L analysis makes worst-case assumptions about task periods (i.e., ratio of two task periods is square root of 2); actual periods are unlikely to resemble the worst case. Conflict-free I/O scheduling treats I/O transactions as non- preemptive and globally synchronizes them in a conflict-free schedule. In the analysis, I/O transactions are regarded as having the highest priority, since this is the most pessimistic assumption for other tasks’ schedulability. This eliminates cross-core inter- ference due to I/O and leads to a decoupling between cores, simplifying the schedulability analysis. In addition, the model assigns CPU utilization budgets to each application (i.e., a group of tasks), yet it schedules tasks globally Acknowledgement: This work was accomplished under ONR N000141410717, N000141612151 and NSF CNS 1302563, 1219064, 1329886 and 1618627, and US ARL W911NF0920053. Any opinions, findings, and conclusions or recommendations expressed here are those of the authors and do not necessarily reflect the views of sponsors. across applications sharing a core. Evaluation showed that this architecture significantly improves schedulability over TDMA and Periodic Server (PS), while maintaining isolation properties. Our utilization bound and global priority assignment with enforced application budgets are complementary; the former is useful early in the development process (indeed, even before coding begins) or during migration, whereas the latter is appli- cable when development is complete and all tasks’ Worst Case Execution Times (WCET)s can be identified accurately. During development, and before the code is instrumented to determine WCETs with interference effects, developers can still execute the code under approximately worst-case conditions and measure processor idle time; this allows a quick and easy estimation of application utilization for comparison with the utilization bound. II. SOFTWARE MIGRATION TO MULTICORE SYSTEMS This paper proposes a task execution model and a schedulabil- ity analysis test, motivated by the need to transition safety-critical software certified on single-core systems to multicore. Toward that end, we make three assumptions motivated by transition realities and design choices: (i) task periods, deadlines, and I/O durations are known since they are tied to system specifications or derived from physical constraints and data size, but our schedulability analysis assumes exact execution times are not yet known, (ii) all I/O transactions are globally scheduled in a conflict-free manner, and (iii) global priority assignment with ap- plication budgets enforced is employed on each core. Our model attempts to remove timing dependencies across applications for their portability. We provide a solution to the schedulability problem. More details of this paper can be found in [2]. A. Task Execution Model Schedulability Analysis with Task Period Data: In this paper, we assume that an allocation of applications to cores has already taken place. We are given M cores. In each core, m, we consider a set, S (m) , of periodic tasks, indexed such that a lower number implies a higher priority in a core. Each task, τ m,i ∈ S (m) , is described by a known period, T m,i , a known relative deadline, D m,i , and a known I/O duration, IO m,i , but WCET of the task, denoted by C m,i , may not be known. Once development is complete, the factors that affect WCETs, including timing interference and delay due to shared resources (e.g., bus, cache, memory), are assumed to be abstracted (by methods such as [3]– [6]) and incorporated in the final WCETs. However, the utilization bound in our analysis allows for unknown WCETs and still obtains a bound on allowable application utilization. Conflict-free I/O: A key requirement for achieving isolation among cores is to ensure non-interference due to I/O. Hence, in this paper, I/O transactions are scheduled such that they are 1261 978-3-9815370-8-6/17/$31.00 c 2017 IEEE