472 • 2020 IEEE International Solid-State Circuits Conference ISSCC 2020 / SESSION 30 / EFFICIENT WIRELESS CONNECTIVITY / 30.7 30.7 A Crystal-Less BLE Transmitter with -86dBm Frequency- Hopping Back-Channel WRX and Over-the-Air Clock Recovery from a GFSK-Modulated BLE Packet Abdullah Alghaihab 1 , Xing Chen 1 , Yao Shi 1 , Daniel S. Truesdell 2 , Benton H. Calhoun 2 , David D. Wentzloff 1 1 University of Michigan, Ann Arbor, MI, 2 University of Virginia, Charlottesville, VA Wireless transceivers traditionally perform local-oscillator (LO) calibration using an external crystal oscillator (XTAL) that adds significant size and cost to a system. Removing the XTAL enables a true single-chip radio, but an alternate means for calibrating the LO is required. Integrated references like on-chip LC [1] or relaxation [2] oscillators are either high power or have PVT sensitivity too high for wireless standards. Multiple crystal-less radios address this challenge [3-6]. [3] replaces the XTAL with an FBAR resonator, which is still not fully integrated. [4-5] recover a reference clock from a received signal but take hundreds of milliseconds to lock and are thus highly susceptible to interference. [6] uses an open-loop LC oscillator to reduce power but has insufficient frequency accuracy for wireless standards. This paper presents a crystal-less transmitter with symmetric over-the-air clock recovery compliant with the BLE standard. The novelty of this work is 1) a frequency-hopping back-channel receiver to detect advertising events from a broadcaster while rejecting interference; 2) an architecture with two fast-locking PLLs and selective baseband filter to recover a reference clock from a received packet and then transmit a GFSK-modulated BLE packet on any channel, and 3) an ADPLL with averaging controller to recover a stable reference from a GFSK- modulated data-whitened signal. The crystal-less transmitter with clock recovery meets all BLE requirements for SIR, making this a robust solution for removing the XTAL even in densely populated networks. The fully integrated crystal-less transceiver is shown in Fig. 30.7.1, which receives and transmits BLE compliant messages. The receiver consists of two RX signal paths mixed down by LO 1 : 1) a back-channel (BC) direct-conversion path for detecting advertising (ADV) events, and 2) a clock-recovery path with an intermediate frequency of 8MHz producing the reference for PLL 1 and PLL 2 . The transmitter comprises a second PLL 2 with LO 2 , a GFSK modulator for open-loop modulation, and a digital PA. Both LOs are on-chip LC oscillators, are trimmed only once for process variation, and when in BC scanning mode operate open- loop without any reference. This is sufficient for a divided LO 2 to clock the digital baseband and for LO 1 to frequency hop between ADV channels in the energy- detection BC path and detect an ADV event (a sequence of 3 packets on the ADV channels). Upon detecting the 3 rd packet in an ADV event, PLL 1 is enabled and locks LO 1 within 50μs to the 8MHz reference recovered from the packet by using a novel averaging controller immune to GFSK-modulated signals. Lock detect of PLL 1 then enables PLL 2 to lock LO 2 in less than 50μs to the 8MHz recovered reference with the LO 2 RF centered on any of the 40 BLE channels. The 8MHz reference is only present while the 3 rd packet is being received, therefore both PLLs must lock before it ends. Finally, after the 3 rd packet ends, the chip switches from RX to TX mode, and LO 2 is used in open-loop to transmit a GFSK-modulated BLE-compliant packet in the desired channel. Figure 30.7.2 shows the state diagram and waveforms for the transient operation of the transceiver detecting an ADV event, recovering the 8MHz reference, and then transmitting a packet. The process begins with the RX back-channel path enabled, scanning the 3 BLE ADV channels for a predefined advertising channel hopping sequence and packet length as in [7]. These channels are CH37, CH38, and CH39 at 2402, 2426, and 2480MHz, respectively. LO 1 hops between channels every 50μs to oversample and detect the energy of ADV packets. Since the BC RX is only scanning for energy in the ADV channels, the LO frequency accuracy is relaxed, and the ADV event can be detected with LO 1 hopping open-loop. In addition, using direct conversion simplifies the baseband filtering and gain and reduces this path’s power consumption. Once the BC demodulator detects the intended ADV event by correlating the digitized signal with programmable templates, the receiver switches to the 2 nd RX path to recover a clock reference from the last incoming packet. This ensures that neither of the two PLLs are enabled until a valid ADV event is detected, eliminating false wakeups and erroneous transmissions. In the clock recovery path, the BLE packet is downconverted to an IF of 8MHz and filtered by a 6 th -order BPF with a bandwidth of 2MHz, removing interferers on adjacent channels. This filter is trimmed only once for process variation. A glitch filter removes short pulses that might exist, e.g. from noise. This signal then becomes the reference for the 2 PLLs, only present while receiving the packet. An 8MHz reference is sufficient for a combined PLL lock time less than one ADV packet, meaning the TX LO is ready before the end of the ADV event. 8MHz also relaxes the required BPF center frequency and quality factor. Using two LOs allows for receiving and transmitting on different BLE channels and for optimizing each PLL controller. Figure 30.7.3 shows a simplified block diagram for both PLLs for reference recovery from the BLE packet and TX transmission. It is a type-I ADPLL with an embedded averaging processing unit (APU) to calibrate the digital control word (DCW) while the PLL is locked. The APU is required because the 8MHz reference is a data-whitened, GFSK-modulated BLE packet, and the FM needs to be removed. The frequency accuracy increases with increasing averaging time, and with enough PLL cycles, the influence from GFSK modulation is minimized. The PLLs in the RX/TX paths are controlled by different frequency control words (FCW) and work at separate frequencies. This reduces mutual coupling between the 2 LOs and enables the TX to transmit in any channel. The LC oscillator (Fig. 30.7.3) uses both NMOS and PMOS cross-coupled pairs for negative resistance and a digitally tuned resistor tail, which helps keep the transistors out of triode and improves phase noise. The 6 th -order active RC BPF is synthesized by cascading three 2 nd -order biquads (Fig. 30.7.3). Each biquad stage is fully differential using the Tow-Thomas topology for its lower sensitivity to parastics. In TX mode, a switched-capacitor digital PA [8] improves efficiency at low power levels. The transceiver was fabricated in a 40nm CMOS process. The measured sensitivity is -86dBm at a BER of 10 -3 (Fig. 30.7.4). The SIR when receiving back-channel messages (Fig. 30.7.4) was measured to be -18dB, -51dB, and <-60dB for the 1 st , 5 th , and 10 th adjacent channels, respectively, meeting the BLE specifications for blocker rejection. The SIR when recovering a reference clock is -20dB and <-60dB for the 1 st and 2 nd adjacent channels, respectively. The NF of the clock recovery path is less than 12dB. This is critical to minimize RMS jitter in the recovered clock, which is measured at 6.5ps and is comparable to crystal oscillators operating at similar frequencies. The GFSK TX output spectrum is shown in Fig. 30.7.5 along with the BLE spectral mask. The measured eye diagram of the TX output packet is shown in Fig. 30.7.5, where the clock driving the GFSK modulator is divided down from open-loop RX LO 1 . The free-running LC oscillator archives -117dBc/Hz phase noise at 1MHz offset. The overall power breakdown of the TRX shows that the RF LOs and buffers consume the highest power percentage (37%) of the total active power of 2.7mW. Figure 30.7.6 shows a comparison between this work and state-of-the-art. This paper reports a new symmetric crystal-less transceiver, where both the received and transmitted messages are compliant with the same communication standard (BLE). This work has the fastest reported frequency calibration time of all crystal- less radios in the comparison table. It outperforms previous designs in interference rejection through high-Q filtering and by enabling PLLs only after detecting a valid ADV event when a BLE packet is known to be present. Figure 30.7.7 shows the die micrograph of the chip, which has an area of 1.33mm 2 . Acknowledgements: This word was supported by NSF under award number 1160483 and 1507192. References: [1] M. S. McCorquodale et al., "A Monolithic and Self-Referenced RF LC Clock Generator Compliant With USB 2.0," IEEE JSSC, vol. 42, no. 2, pp. 385-399, Feb. 2007. [2] N. Liu et al., "A 2.5 ppm/°C 1.05-MHz Relaxation Oscillator With Dynamic Frequency-Error Compensation and Fast Start-Up Time," IEEE JSSC, vol. 54, no. 7, pp. 1952-1959, July 2019. [3] B. Wiser et al., "A 1.53 mm 3 Crystal-Less Standards-Compliant Bluetooth Low Energy Module for Volume Constrained Wireless Sensors," IEEE Symp. VLSI Circuits, pp. C84-C85, 2019. [4] W. Chen et al., "A 2.4 GHz Reference-Less Receiver for 1 Mbps QPSK Demodulation," IEEE TCAS I, vol. 59, no. 3, pp. 505-514, March 2012. [5] F. Maksimovic et al., "A Crystal-Free Single-Chip Micro Mote with Integrated 802.15.4 Compatible Transceiver, sub-mW BLE Compatible Beacon Transmitter, and Cortex M0," IEEE Symp. VLSI Circuits, pp. C88-C89, 2019. [6] L. Chuo et al., “A 915MHz Asymmetric Radio Using Q-Enhanced Amplifier for a Fully Integrated 3×3×3mm 3 Wireless Sensor Node with 20m Non-Line-of-Sight Communication," ISSCC, pp. 132-133, Feb. 2017. [7] A. Alghaihab et al., "Enhanced Interference Rejection Bluetooth Low-Energy Back-Channel Receiver With LO Frequency Hopping," IEEE JSSC, vol. 54, no. 7, pp. 2019-2027, July 2019. [8] X. Chen et al., "Analysis and Design of an Ultra-Low-Power Bluetooth Low- Energy Transmitter With Ring Oscillator-Based ADPLL and 4 X Frequency Edge Combiner," IEEE JSSC, vol. 54, no. 5, pp. 1339-1350, May 2019. 978-1-7281-3205-1/20/$31.00 ©2020 IEEE Authorized licensed use limited to: University of Michigan Library. Downloaded on May 27,2020 at 18:26:00 UTC from IEEE Xplore. Restrictions apply.