185 Estonian Journal of Engineering, 2011, 17, 3, 185–200 doi: 10.3176/eng.2011.3.02 Hierarchical physical defect reasoning in digital circuits Sergei Kostin, Raimund Ubar, Jaan Raik and Marina Brik Department of Computer Engineering, Tallinn University of Technology, Ehitajate tee 5, 19086 Tallinn, Estonia; {skostin, raiub, jaan, brik}@pld.ttu.ee Received 7 February 2011, in revised form 14 June 2011 Abstract. We propose a hierarchical physical defect-oriented approach for fault diagnosis in combinational digital circuits. We present the circuit as a network of modules. As modules we consider either library components (e.g. complex gates) of digital circuits or arbitrary subcircuits. The higher level fault diagnosis is carried out in two phases. In the first phase, faulty modules are located by cause–effect analysis using high-level faulty module dictionary. The size of the dictionary depends linearly on the number of modules in the circuit. In the second phase, the set of suspected faulty modules is pruned by reasoning of the defective behaviour. At the lower level, the physical defects are directly located in suspected faulty modules using defect libraries of the modules or by effect–cause reasoning inside the module. The proposed approach to fault diagnosis helps to cope with the growing complexities of digital circuits. The experimental results show high module-level diagnostic resolution of the proposed approach. Key words: digital circuits, physical defects, fault models, fault diagnosis, diagnostic resolution. 1. INTRODUCTION Rapid advances in the areas of nanoscale electron technology and design automation tools enable engineers to design larger and more complex integrated circuits. On the other hand, the increasing integration densities pose severe problems with respect to the quality assurance. The quality and reliability of microelectronic circuits depend essentially on the efficiency of debug and diagnosis of failures in circuits. Traditional approaches to diagnosis of digital circuits are based on gate-level models [ 1–4 ]. However, due to the continuous increasing of the gate count in circuits under diagnosis, the gate-level methods are becoming less efficient and obsolete. Two main trends can be observed when searching solutions for the problems of testing and diagnosis: defect-orientation, and high-level modelling [ 5 ]. The trend towards high-level modelling helps us to cope with the complexity, but