Frame-level Heuristic Scheduling Multi-view Video Coding on Symmetric Multi-core Architecture Yi Pang pangy@mails.tsinghua.edu.cn Jiangtao (Gene) Wen jtwen@tsinghua.edu.cn Lifeng Sun sunlf@tsinghua.edu.cn Weidong Hu mail@hwd.name Shiqiang Yang yangshq@tsinghua.edu.cn Tsinghua National Laboratory for Information Science and Technology(TNList)) Computer Science Dept.,Tsinghua Uni. Beijing, China Abstract In this paper, we propose a frame-level heuristic schedul- ing parallel emerging Multi-view Video Coding (MVC) us- ing Directed Acyclic Graph (DAG) on Intel multi-core pro- cessor. We illustrate the reason to choose heuristic schedul- ing and formulate the problem. Through defining depen- dent degree and concurrent degree, we demonstrate why to choose frame as parallel granularity. Experimental results demonstrate the effectiveness and scalability of our parallel MVC. 1 Introduction In spite of the rapid improvement of micro-processor technology, video encoding, which has evolved in the last two decades from MPEG-2 to Advanced Video Cod- ing (AVC), as well as Multi-view Video Coding (MVC) and Scalable Video Coding (SVC), remains outside of the realm of practicality on even the most cutting-edge micro- processor platforms. Relative to the demands on processor and I/O performance, processor capabilities, albeit advanc- ing rapidly, remains lagging behind the ever-higher require- ments. This situation is illustrated in Figure 1, which shows the rate of increase for the relative computation complex- ity of different video coding standards, as well as the rate of growth in computational capabilities for uni-core and multi- core micro-processors over the same period of time. The rates of growth in both cases are normalized to the year 1995, when MPEG-2 was first widely adopted. The challenge however, in utilizing multi-core technol- ogy for video encoding, is to “map” the application onto a multi-core processor, so that the cores are utilized to the Figure 1. Development of Video Compression and Processor Technologies fullest extent possible, while unnecessary data exchange be- tween the cores and especially between the processor and external, off-chip memory are eliminated to the greatest ex- tent. Video encoding involves computation intensive tasks that can be parallelized. The frequency and scope of these operations however, are usually context dependent, which makes it impossible for a static scheduling algorithm to achieve optimized performance partitioning video encod- ing onto multi-core processors. In addition, video encoding presents numerous possibilities of parallelizing the tasks at different granularities and different levels of the syntax hier- archy, usually with different performance/complexity trade- offs. Parallel architecture for video encoding has been an ac- tive research topic for well over a decade, and will continue to be so in the foreseeable future. Interested readers may re- 2305 978-1-4244-5654-3/09/$26.00 ©2009 IEEE ICIP 2009