JOURNAL OF ELECTRONICTESTING:Theory and Applications, 3, 397-406 (1992) 9 1992 Kluwer Academic Publishers, Boston. Manufacturedin The Netherlands. Design of ICs Applying Built-In Current Testing* WOJCIECH MALY AND MAREK PATYRA Electrical and Computer Engineering Department, Carnegie Mellon University, Pittsburgh, PA 15213 Received February 5, 1992. RevisedAugust 24, 1992. Editor: C.E Hawkins Abstract. Built-in Current (BIC) sensors have proven to be very useful in testing static CMOS ICs. In a number of experimental ICs BIC sensors were able to detect small abnormal Ioo Q currents. This paper discusses the design of the circuit under test and Built-in Current (BIC) sensors, which provide: maximum level of defect detectability, minimum impact of BIC sensor on the performance of the circuit under test and minimum area overhead needed for BIC sensors implementation. Keywords: Built-in testing, BIC-testing, current testing. 1. Introduction IDD Q testing [1]-[4] was found to be very useful in detecting large classes of faults occurring in tested ICs [5], [6]. Many researchers, as well as years of experi- ence, have shown that this testing technique, especially useful in static CMOS circuits, can provide a quality of testing unattainable by any other testing methods [4], [7]. It was also recognized that implementation of IDD o testing has not been straightforward because it has required both special purpose testing hardware and a significant decrease in the testing rate [7]. To over- come these shortcomings a Built-in Current (BIC) testing technique was proposed [7], [8] and a number of experimental IC chips with BIC sensors were fabri- cated and tested [9]-[11]. The BIC testing implemented on these chips applies current sensors to monitor the amount of quiescent current in the power lines of the functional units under the test. Since the vast majority of defects occurring in the typical process causes an increase in the quiescent current [5], [7], BIC sensors can be used effectively for testing purposes. Fabrication experiments conducted in the last cou- ple of years, have fully confirmed the basic concept of BIC testing. They also helped to answer three key questions: (1) how to minimize the impact of the BIC sensor on the performance of the functional unit under test; (2) how to optimize the BIC sensor design from *This research was supported by NSF Grant MIP8822805. the defect detectability point of view; and (3) how to optimize the circuit under test to obtain the maximum level of defect detectability at the same time minimiz- ing area overhead needed for BIC sensors. The goal of this article which is an extended version of [5] is to summarize the information addressed by the above questions. 2. BIC Testing The basic idea of BIC testing is simple and has been explained in a number of articles [5], [7], [8], [12]. This section summarizes the key elements of the BIC testing methodology published in the past and also dis- cusses a newer version of the BIC sensor design. 2.1. Implementation of BIC Testing Figure la explains the basic structure of the BIC sen- sor. It is composed of a voltage drop device and a voltage comparator. These basic components of any BIC sensor are arranged such that at the end of each clock cycle the virtual ground voltage, VEND, is compared with the voltage reference, Vre f. The value of Vref is chosen such that VGN D < Vre f for defect free func- tional units and VGN D > Vre f for those units where the quiescent current indicates an occurrence of a defect. It is also possible to locate the voltage drop device 111