Power Noise Suppression Technique using Active Decoupling Capacitor for TSV 3D Integration Tien-Hung Lin, Po-Tsang Huang, and Wei Hwang Department of Electronics Engineering & Institute of Electronics, and Microelectronics and Information Systems Research Center, National Chiao Tung University, HsinChu 300, Taiwan ABSTRACT In three-dimensional (3D) integration, the increasing supply current through both package and through-silicon-via (TSV) would lead to a large simultaneous switching noise potentially. In this paper, a noise suppression technique using low power active decoupling capaCitors (DECAPs) is proposed for TSV 3D integration. Through the latch-based noise detection circuitry, the power supply noise can be detected and regulated via active DECAPs. Based on UMC 65nm CMOS technology and TSV model at 1V supply voltage, the proposed noise suppression circuit can realize maximum 7.4dB supply noise reduction and 12X boost fact at the resonant frequency. I. INTRODUCTION Three-dimensional (3D) integration technology can provide enormous advantages in achieving multi-functional integration, improving system speed and reducing power consumption for future generations of ICs [1]. However, stacking multiple dies would face a severe problem of the power integrity [2]. Fig.1 shows the power integrity for the TSV 3D integration. It is shown that heavy current density of through-silicon-via (TSVs) and packages exists in the power network and further increases the power supply noise. Moreover, the supply impedance response is dominated by both the packages and TSVs [3]. In view of these, noise suppression will become one of the critical design problems for TSV 3D integration. To suppress the power noise, decoupling capaCitors (DECAPs) are widely used. DECAPs perform as a local reservoir of charge, which is released when the current load varies. Since the inductance of packages scales slowly, the DECAPs significantly affect the design of the powerlground (PIG) networks in high performance ICs and TSV 3D integration. At higher frequencies, DECAPs are distributed on chips to effectively 978-1-4244-6683-2/101$26.00 ©2010 IEEE 209 TSV Fig. 1: Power integrity for TSV 3D integration. Heavy current density of power network manage the power supply noise. However, the usage of the on-chip passive DECAPs is limited by two major constraints, including a great amount of gate tunneling leakage and large area occupation [4]. Therefore, current suppression techniques have been proposed to reduce power supply noise, and the resonant supply noise is suppressed via the delay-line-based and OP-based detection circuits with switched DECAPs, respectively [4, 5]. However, the efficiency of these noise suppression techniques would be reduced significantly by the leakage current in nano-scale technologies. In this paper, a noise suppression technique is proposed for TSV 3D integration based on UMC 65nm CMOS technology. This noise suppression technique reduces the supply noise using a latch- based comparator and switched DECAPs. II. Power Noise Suppression for 3D Integration Depending on the heavy current loading of PIG networks in 3D integration, the supply noise is a serious problem for power integrity. In view of this, Fig. 2 shows the proposed architecture of the noise suppression technique to reduce the supply noise. This architecture contains four blocks: a low pass filter, a latch-based comparator, a charge pump, and switched DECAPs. The prior three blocks are designed to detect the resonant supply noise and to control the switches of the switched DECAPs. The details of each block are described as follows.