Abstract—Error correcting codes are used for detection and correction of errors in digital communication system. Error correcting coding is based on appending of redundancy to the information message according to a prescribed algorithm. Reed Solomon codes are part of channel coding and withstand the effect of noise, interference and fading. Galois field arithmetic is used for encoding and decoding reed Solomon codes. Galois field multipliers and linear feedback shift registers are used for encoding the information data block. The design of Reed Solomon encoder is complex because of use of LFSR and Galois field arithmetic. The purpose of this paper is to design and implement Reed Solomon (255, 239) encoder with optimized and lesser number of Galois Field multipliers. Symmetric generator polynomial is used to reduce the number of GF multipliers. To increase the capability toward error correction, convolution interleaving will be used with RS encoder. The Design will be implemented on Xilinx FPGA Spartan II. Keywords—Galois Field, Generator polynomial, LFSR, Reed Solomon. I. INTRODUCTION IGITAL Communication system is immune to errors, but there exit some errors which result in wrong data reception by receiver. Thus, transmitter has to send same data again to compensate for errors. This results in wastage of resources. To reduce the burden over transmitter to transmit same data again error correcting codes are used for detection and correction of errors that are introduced during transmission of data from source to destination. Reed Solomon codes are non-binary BCH error correcting codes.In 1959, Irving Reed and Gus Solomon described a new class of error- correcting codes called Reed-Solomon codes [1].Originally Reed-Solomon codes were constructed and decoded through the use of finite field arithmetic. Reed Solomon codes are burst error correcting codes. RS codes detect and correct errors on symbol level i.e. if there is any error of 1-bit or 2-bit or m bit in symbol of m bit then these error correcting codes will correct the complete symbol. Before the transmission of data, RS encoder appends some parity bits to the data so that at decoder these bits can be used for error detection and correction. Algorithm used for encoding RS codes is very complex as calculations are done over Galois field. The complexity can be reduced with use of symmetric coefficients of generator Amandeep Singh is Postgraduate Student at Electronics and Communication Engineering department, UCoE, Punjabi University Patiala, Punjab, India (e-mail: amandeep.singh568@gmail.com) Mandeep Kaur is Assistant Prof. at Electronics and Communication Engineering department, UCoE, Punjabi University Patiala, Punjab, India (e- mail: ermandeep0@gmail.com). polynomial [2]. Further, multiplication values can be optimized which reduces the number of AND gates and multiplication can be implemented with XOR gates only if one of the operand is known [3]. Objective of this work is to implement Reed Solomon encoder with symmetric generator polynomial and globally optimized Galois Field multipliers [4]. The design was implemented on Xilinx Spartan 2e FPGA. This paper goes over with theory behind Reed-Solomon encoding, Architecture of implemented RS encoder and future scope of the study. II. BASICS OF REED SOLOMON FEC CODES. Reed Solomon codes are forward error correcting codes that can be specified as RS (n,k) where n is the size of code word generated by RS encoder and k is size of data input to RS encoder. The difference between number of symbols out from RS encoder and number of symbols input to RS encoder is called parity symbols 2t. Each symbol is formed from m bits. Fig 1 below shows the code word of Reed Solomon code. Fig. 1 Code word generated by Reed Solomon encoder k: Symbols input to RS encoder; n: Symbols output from RS encoder (n = 2 m – 1); 2t: parity symbols = n – k; m: Size of each symbol Data stream of bits is divided into k symbols each being m bit long. 2t parity symbols are appended to k symbols to give n symbols of RS code. Data symbol is represented in polynomial form with highest power of x representing MSB and lowest power of x representing LSB. Input data symbols will contain powers from 0 to k – 1 (LSB to MSB) and output symbols will contain powers from 0 to n-1 (LSB to MSB) [5]. Reed Solomon codes are constructed using a special type of polynomial called generator polynomialg(x) having α as its one of root is given by (1) and (2). g(x) = (x+α) (x+α 2 ) (x+α 3 ) . . . . (x+α 2t ) (1) ∏ α     (2) The code word polynomial c(x) is generated by equation below: Design and Implementation of Reed Solomon Encoder on FPGA Amandeep Singh, Mandeep Kaur D World Academy of Science, Engineering and Technology International Journal of Information and Communication Engineering Vol:7, No:9, 2013 1248 International Scholarly and Scientific Research & Innovation 7(9) 2013 scholar.waset.org/1307-6892/17229 International Science Index, Information and Communication Engineering Vol:7, No:9, 2013 waset.org/Publication/17229