3D Integration Technologies Using Self-Assembly and Electrostatic Temporary Multichip Bonding T. Fukushima 1 , H. Hashiguchi 2 , J. Bea 1 , M. Murugesan 1 , K.-W. Lee 1 , T. Tanaka 2, 3 , and M. Koyanagi 1 1 New Industry Creation Hatchery Center (NICHe), Tohoku University, 2 Graduate School of Engineering, Tohoku University 3 Graduate School of Biomedical Engineering, Tohoku University, Phone: +81-22-795-4119; E-mail: fukushima@bmi.niche.tohoku.ac.jp Abstract We developed a new chip-to-wafer 3D integration technology using self-assembly and electrostatic (SAE) bonding. High-throughput multichip self-assembly with a high alignment accuracy within 1 m was achieved by the SAE bonding technique. Self-assembled known good dies (KGDs) were temporarily bonded on SAE carriers by electrostatic bonding force. We implemented multichip transfer processes twice and then formed through-silicon vias (TSVs) for the self-assembled KGDs to fabricate 3D-stacked chips with Cu-TSVs and Cu/SnAg microbumps. By using the new multichip-to-wafer 3D integration process with SAE bonding, we obtained good electrical characteristics from the self-assembled KGDs having Cu-TSVs and Cu/SnAg microbumps. Introduction 3D system integration using wafer bonding with vertical buried interconnections, later called TSVs, has been proposed in the late 1980s [1]. Wafer-to-wafer 3D integration has been studying since the mid-1990s [2]-[12]. In addition, chip-to- wafer 3D integration with TSVs has been attracting attention since the mid-2000s [13]-[14]. As shown in Fig.1, we have proposed advanced multichip-to-wafer 3D integration including reconfigured wafer-to-wafer approach using self- assembly with liquid surface tension as a driving force in order for creating a highly integrated 3D and hetero systems in a chip [15]-[28]. We call them 3D super chip, where TSVs and metal microbumps vertically and electrically connect between various kinds of thin KGDs three-dimensionally stacked in layers. The multichip self-assembly has a great advantage in high alignment accuracy, and in addition, it can solve a serious trade-off problem between alignment accuracy and alignment throughput. In the advanced multichip-to-wafer 3D integration using the multichip self-assembly, temporary multichip bonding/debonding is a key technology. Electrostatic chucking is well-known to be a wafer handling method. Versatile thin wafer handling systems using electrostatic wafer carriers have recently reported for 3D integration [29]. In the present paper, we apply a new electrostatic multichip bonding/debonding technique to self- assembled-based 3D integration. We call this SAE (self- assembly and electrostatic) bonding in which SAE carrier wafers have unipolar or bipolar electrodes for electrostatic temporary bonding/debonding in addition to hydrophilic/hydrophobic areas for self-assembly. Here, multichip transfer, multichip thinning, TSV formation, and multichip 3D stacking are demonstrated by combining them with SAE bonding. 3. Multichip thinning 4. TSV and/or microbump formation 2. Microbump bonding (multichip transfer) Interposer wafer Interposer wafer Interposer wafer Reconfigured wafer-to-wafer 3D Integration Direct multichip-to-wafer 3D integration 1. Multichip self-assembly (Face-down) 2. Microump bonding TSV Liquid Via-Last Via-Middle Interposer wafer Liquid Interposer wafer Interposer wafer Support wafer Via-Last Via-Middle NCF Microbump Underfill 5. 3D integration 1. Multichip self-assembly (Face-up) Support wafer Interposer wafer Interposer wafer Interposer wafer Interposer wafer Figure 1. Self-assembly-based multichip-to-wafer 3D integration categories we have developed so far. Process Flow of 3D Integration Using SAE Bonding First, unipolar or bipolar electrodes for electrostatic temporary bonding/debonding and the subsequent hydrophilic/hydrophobic areas for self-assembly were formed on carrier wafers called SAE carriers. In these experiments, we used KGDs having Cu wirings (M1 layer) covered with plasma-TEOS oxides on the surface. The KGDs were sequentially self-assembled with water droplets in a face-up bonding manner to the SAE carriers by a robotic pick-and- place method using a high-speed chip self-assembler. Then, the KGDs were temporarily bonded to the SAE carriers by electrostatic bonding force. After that, SAE carriers were aligned to the corresponding support wafers, and then, the many KGDs were debonded form the SAE carriers and transferred to the support wafers on which a high-heat- resistance temporary adhesive was coated. The following was the so-called via last / backside via process, where, the thick KGDs were first thinned down to approximately 30 m. Cu- TSVs were 10 m in diameter and Cu/SnAg microbump were 20/40 m in size/pitch. After TSV/microbump formation, the support wafer having the many KGDs were aligned and bonded to target interposer wafers through a non-conductive film (NCF) to give multichip transfer onto the interposer wafers. By repeating the sequences, multiple stacked 3D super chips were obtained. Figure 2 shows the total 978-1-4799-0232-3/13/$31.00 ©2013 IEEE 58 2013 Electronic Components & Technology Conference