VOL. 11, NO. 5, MARCH 2016 ISSN 1819-6608 ARPN Journal of Engineering and Applied Sciences © 2006-2016 Asian Research Publishing Network (ARPN). All rights reserved. www.arpnjournals.com 3137 VARIABILITY ANALYSIS OF PROCESS PARAMETERS ON SUBTHRESHOLD SWING IN VERTICAL DG-MOSFET DEVICE K. E. Kaharudin 1 , F. Salehuddin 1 , A. H. Hamidon 1 , A. S. M. Zain 1 , M. N. I. Abd Aziz 1 and I. Ahmad 2 1 Centre for Telecommunication Research and Innovation (CeTRI), Faculty of Electronics and Computer Engineering, Universiti Teknikal Malaysia Melaka (UTeM), Hang Tuah Jaya, Durian Tunggal, Melaka, Malaysia 2 Centre for Micro and Nano Engineering (CeMNE), College of Engineering, Universiti Tenaga Nasional (UNITEN), Kajang, Selangor, Malaysia Email ID: khairilezwan@yahoo.com.my ABSTRACT As the MOSFET’s size is expected to be shrunk every year, it is difficult to mitigate the short channel effect (SCE) issues arising in the device. The conventional MOSFET’s structure is no longer practical to apprehend these types of issues, especially for a device with a very small gate length (Lg). The SCE issues happen due to the reduction of the gate length (Lg), which causes the distance between the source and the drain region to become too close to each other. As a consequence, it causes the charge sharing effects between source and drain region that eventually leads to higher subthreshold swing (SS). A steep SS value around 55 to 65 mV/dec is desired in MOSFET device for faster switching operation. Therefore, a new architecture of Vertical Double Gate (DG) MOSFET device is proposed to circumvent these issues. Besides that, the process parameter variations in the device are also considered as one of the important factors that significantly affect the SS value. In this paper, an attempt to analyze the variability of multiple process parameters towards the SS value in 12nm gate length (Lg) vertical DG-MOSFET device has been made. At the end of the experiments, it was found that the most dominant process parameter that contributed a large effect on SS value was halo implantation tilt angle. The lowest possible value of SS was observed to be 62.52 mV/dec with signal-to-noise ratio (SNR) of -35.83 dB. Keywords: ANOVA, DG-MOSFET, subthreshold swing, taguchi method. INTRODUCTION The Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is widely applied for amplifying and switching electronics signals. In MOSFET devices, a voltage potential that appears on the oxide-insulated gate electrode is capable of creating a conducting channel between the source and the drain region. The channel can be either n-type or p-type depending on the type of dopant used in the substrate. It is commonly recognized as a NMOS and a PMOS device. The source region is the source of charge carrier, either electrons or holes flow through the channel [1]. Meanwhile, the drain region is where the charge carrier leaves the channel. Nowadays, MOSFET devices are actively being scaled down for miniaturization of integrated circuit (IC). By reducing the size of transistors and interconnectors, more circuits can be fabricated on each silicon wafer. Thus, the price of each circuit will become cheaper and affordable. However, miniaturization in MOSFET device has its side effect, which is known as short channel effects [2]. Many electronics scientists and researchers have conducted research on suppressing the SCEs in the nano- scale MOSFET devices. They tend to come out with new ideas of architecture and approach on how to mitigate the SCE issues. Through the implementation of vertical DG- MOSFET architecture, the effective channel length (Lc) is no longer dependent on the gate length (Lg). The height of silicon pillars acts as a control factor to vary the size of effective channel length [3]. Therefore, various SCE problems are still possible to be mitigated even at small gate length (Lg) such 12nm of Lg. However, there is an important aspect that has to be considered, which is known as process parameter variations. Process parameter variations occur in every type of MOSFET device. These variations would affect the output responses (electrical characteristics) of the MOSFET devices. They may cause the degradation of overall MOSFET’s electrical performance [4, 5]. In this paper, the 12nm gate length of vertical DG-MOSFET was successfully designed by using software SILVACO Technology Computer Aided Design (TCAD). The input process parameters that contribute the most significant impact on the SS value were investigated by utilizing L27 orthogonal array Taguchi method. The subthreshold swing is an important response which indicates the scalability limit of the MOSFET. It also shows how much change in the gate voltage (VG) is required to change drain current (ID) by one decade [6]. Vertical Dg-MOSFET design using Silvaco TCAD A P-type silicon with <100> orientation was used as the main substrate for this experiment. A different silicon orientation will give different substrate properties such as device mobility. Normally, P-type silicon with <100> orientation is used for MOSFET fabrication process due to a significant improvement in the effective maximum mobility for the n-MOSFETs with a channel along the 100 directions and the channel direction had no effect on the noise level and the performances of the devices [7]. The silicon was etched in order to form a pillar or ridge that separated the two gates. The combination of buried oxide (BOX) and the polysilicon layer formed an enhanced channel that was capable of